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Execution unit in Verilog ?

Started by Ben A. Abderazek November 18, 2004
Dear helper,
I am implementing a new processor in verilog.
I am no near the execution unit implementation!!
Does any one have (or know) a full design of RISC-style instructions
execution unit in verilog.
I am planning to implement 1 ALU unit, 1 Branch unit, 1 SET unit, and 1
LDST unit.
I really need the unit..please help.
/Ben
UEC, IS , Tokyo





Ben A. Abderazek wrote:

> Dear helper,
> I am implementing a new processor in verilog.
> I am no near the execution unit implementation!!
> Does any one have (or know) a full design of RISC-style instructions
>execution unit in verilog.
> I am planning to implement 1 ALU unit, 1 Branch unit, 1 SET unit, and 1
>LDST unit.
> I really need the unit..please help.
> /Ben
> UEC, IS , Tokyo
How about Risc100 @ opencores.org ? Full GNU sopport
as well.

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If you google you shall find.

As well, the XR16 in the XSOC Kit (http://fpgacpu.org/xsoc/) includes a
Verilog implementation.

As a schematic design came first, it is quite structural, and so I don't put
it forth as a *good* example of Verilog.

There is also a simpler, annotated Verilog RISC processor datapath in the
article at http://www.fpgacpu.org/papers/soc-gr0040-paper.pdf. See also the
accompanying slides http://www.fpgacpu.org/papers/soc-gr0040-slides.pdf.

At least one Verilog textbook includes a RISC processor design.

Jan Gray


> There is also a simpler, annotated Verilog RISC processor datapath in
the
> article at http://www.fpgacpu.org/papers/soc-gr0040-paper.pdf. See also
the
> accompanying slides http://www.fpgacpu.org/papers/soc-gr0040-slides.pdf.
Many thanks Gray. I found the DOCs interesting.
/Ben
UEC-IS