Hi everyone!

I'm "new" here. I've been keeping in the shadows for some time, scourging the group for advice when noone was looking. I always managed to find a piece of advice from you people to help me along. Many thanks for that. But now I think I've hit a wall.

I'm working on a design with the LPC1776 with a slab of SDRAM along with it. This is my first "sorta" high-speed design. I've already routed my 2-layer board (please don't faint), matching all my traces within 20-25mm and flooding with grounds top and bottom and with vias going along with any signal layer transitions. I'm also way below the wavelength length-wise (133MHz, 1/10@FR4 = 10cm), so even without termination resistors (except clock) I should be fine (I hope!).

After routing I wanted to do some math on the timing budget, and I'm baffled. Looking at the EMC timing diagram (LPC177x/178x datasheet [http://www.nxp.com/documents/data_sheet/LPC178X_7X.pdf], page 85) the read cycle and write cycle parameters make no sense.

For example, the read cycle - The setup time is stated as 5.2ns to 1.5ns (wrong order?). By my math it's doable:

Tcyc - RAM access time - EMC setup time = 12.5ns - 6ns - 5.2ns = 1.3ns margin for flight-time

But the hold time is a different beast. Every SDRAM I've looked at generally specifies its hold time in the order of 2-3ns for output data, but the EMC specifies it as requiring a minimum of 3.7 to 5.2ns to capture data. Even in the best-case of 3.7ns that's 700ps short of the mark.

Same goes for the write hold time. The SDRAM requires a hold for a nanosecond, but the EMC specifies it as only 0.2 to 1.6 ns. Only 200ps hold time in the worst-case or am I reading this stuff all wrong?

I've looked at the different clock delay options that would maybe remedy the situation by shifting the setup and hold-times around a bit, dug up all sorts of dirt, but I cannot find any decent explanations anywhere. The user manual breezes by it with one tiny paragraph. I even grabbed the ARM PrimeCell MultiPort Memory
Controller (PL176) reference manual in the hopes it would shed some light on the subject, but it is equally confusing.

How can you meet such setup and hold times?

So, basically my impression is that the EMC, with no clock delays set, is way off specs to even interface with an off-shelf SDRAM or am I the one that is way off specs? :)

Any guidance that anyone could offer would be much appreciated here or could throw me a stick that would point me in the right direction :)

Regards,
Matt

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Hi Matt,

Sorry I can't help directly but since you've had no replies, I thought you might find this thread on lpcware helpful.

http://www.lpcware.com/content/forum/dk-57vts-lpc1788-configuring-emc-sdram

Nick
--- In l..., "teeysensei" wrote:
>
> Hi everyone!
>
> I'm "new" here. I've been keeping in the shadows for some time, scourging the group for advice when noone was looking. I always managed to find a piece of advice from you people to help me along. Many thanks for that. But now I think I've hit a wall.
>
> I'm working on a design with the LPC1776 with a slab of SDRAM along with it. This is my first "sorta" high-speed design. I've already routed my 2-layer board (please don't faint), matching all my traces within 20-25mm and flooding with grounds top and bottom and with vias going along with any signal layer transitions. I'm also way below the wavelength length-wise (133MHz, 1/10@FR4 = 10cm), so even without termination resistors (except clock) I should be fine (I hope!).
>
> After routing I wanted to do some math on the timing budget, and I'm baffled. Looking at the EMC timing diagram (LPC177x/178x datasheet [http://www.nxp.com/documents/data_sheet/LPC178X_7X.pdf], page 85) the read cycle and write cycle parameters make no sense.
>
> For example, the read cycle - The setup time is stated as 5.2ns to 1.5ns (wrong order?). By my math it's doable:
>
> Tcyc - RAM access time - EMC setup time = 12.5ns - 6ns - 5.2ns = 1.3ns margin for flight-time
>
> But the hold time is a different beast. Every SDRAM I've looked at generally specifies its hold time in the order of 2-3ns for output data, but the EMC specifies it as requiring a minimum of 3.7 to 5.2ns to capture data. Even in the best-case of 3.7ns that's 700ps short of the mark.
>
> Same goes for the write hold time. The SDRAM requires a hold for a nanosecond, but the EMC specifies it as only 0.2 to 1.6 ns. Only 200ps hold time in the worst-case or am I reading this stuff all wrong?
>
> I've looked at the different clock delay options that would maybe remedy the situation by shifting the setup and hold-times around a bit, dug up all sorts of dirt, but I cannot find any decent explanations anywhere. The user manual breezes by it with one tiny paragraph. I even grabbed the ARM PrimeCell MultiPort Memory
> Controller (PL176) reference manual in the hopes it would shed some light on the subject, but it is equally confusing.
>
> How can you meet such setup and hold times?
>
> So, basically my impression is that the EMC, with no clock delays set, is way off specs to even interface with an off-shelf SDRAM or am I the one that is way off specs? :)
>
> Any guidance that anyone could offer would be much appreciated here or could throw me a stick that would point me in the right direction :)
>
> Regards,
> Matt
>

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Thanks Nick.

I got somewhere with my maths though. Have a look people,

setup-margin = Tclk - Td - Tsu - TOF + Tskew
hold-margin = Th(tx) - Th(rx) + TOF - Tskew

RAM Tac = Td = 6ns, Tsu = 2ns, Th = 2.5ns, all the other numbers are from the LPC177x/178x datasheet, page 85, command delayed mode table 19.

1.) Data write:

RAM(su-margin) = 12.5 - 7.3 - 2 - 0.2 = 3 + Tskew
RAM(h-margin) = 0.2 - 1 + 0.2 = -0.6 - Tskew

Right, so we can solve that with the EMC getting clocked last - a negative clock skew. There's enough room in setup, or use command delay mode.

2.) Data read:

EMC(su-margin) = 12.5 - 6 - 5.3 - 0.2 = 1ns + Tskew
EMC(h-margin) = 2.5 - 5.2 + 0.2 = -2.5 - Tskew

Here the sunshine sets. By these margins there is no way you can compensate for the hold margin. Trying to delay the RAM (EMC clocked first - negative skew) will break the setup margin. The only way to fix what's broken is to throttle down to about 70MHz (~15ns period).

Also, by looking at the LPC177x/178x user manual, page 157, fig. 13, there is no way to delay the SDRAM without delaying the EMC along with it - except by clocking the SDRAM out from CLKOUT1, since CLKOUT0, already delayed, leads right back into the EMC as the feedback clock.

If someone has got a feel for this, please do check out my math and the values I used. I do think I got the equations right, although I'm no way an expert at this stuff.

All I could find on the net were tried-out numbers and guesses, it sure would be nice to have some concrete numbers...

Thanks for any help in advance!

Regards,
Matt

--- In l..., "nickulli" wrote:
>
> Hi Matt,
>
> Sorry I can't help directly but since you've had no replies, I thought you might find this thread on lpcware helpful.
>
> http://www.lpcware.com/content/forum/dk-57vts-lpc1788-configuring-emc-sdram
>
> Nick
> --- In l..., "teeysensei" wrote:
> >
> > Hi everyone!
> >
> > I'm "new" here. I've been keeping in the shadows for some time, scourging the group for advice when noone was looking. I always managed to find a piece of advice from you people to help me along. Many thanks for that. But now I think I've hit a wall.
> >
> > I'm working on a design with the LPC1776 with a slab of SDRAM along with it. This is my first "sorta" high-speed design. I've already routed my 2-layer board (please don't faint), matching all my traces within 20-25mm and flooding with grounds top and bottom and with vias going along with any signal layer transitions. I'm also way below the wavelength length-wise (133MHz, 1/10@FR4 = 10cm), so even without termination resistors (except clock) I should be fine (I hope!).
> >
> > After routing I wanted to do some math on the timing budget, and I'm baffled. Looking at the EMC timing diagram (LPC177x/178x datasheet [http://www.nxp.com/documents/data_sheet/LPC178X_7X.pdf], page 85) the read cycle and write cycle parameters make no sense.
> >
> > For example, the read cycle - The setup time is stated as 5.2ns to 1.5ns (wrong order?). By my math it's doable:
> >
> > Tcyc - RAM access time - EMC setup time = 12.5ns - 6ns - 5.2ns = 1.3ns margin for flight-time
> >
> > But the hold time is a different beast. Every SDRAM I've looked at generally specifies its hold time in the order of 2-3ns for output data, but the EMC specifies it as requiring a minimum of 3.7 to 5.2ns to capture data. Even in the best-case of 3.7ns that's 700ps short of the mark.
> >
> > Same goes for the write hold time. The SDRAM requires a hold for a nanosecond, but the EMC specifies it as only 0.2 to 1.6 ns. Only 200ps hold time in the worst-case or am I reading this stuff all wrong?
> >
> > I've looked at the different clock delay options that would maybe remedy the situation by shifting the setup and hold-times around a bit, dug up all sorts of dirt, but I cannot find any decent explanations anywhere. The user manual breezes by it with one tiny paragraph. I even grabbed the ARM PrimeCell MultiPort Memory
> > Controller (PL176) reference manual in the hopes it would shed some light on the subject, but it is equally confusing.
> >
> > How can you meet such setup and hold times?
> >
> > So, basically my impression is that the EMC, with no clock delays set, is way off specs to even interface with an off-shelf SDRAM or am I the one that is way off specs? :)
> >
> > Any guidance that anyone could offer would be much appreciated here or could throw me a stick that would point me in the right direction :)
> >
> > Regards,
> > Matt
>

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