Il 03/10/2012 21:35, Jean-Sebastien Stoezel ha scritto:
> Schematic attached, check page 2.
There is no schematic attached. You can send me it directly at
m...@micronengineering.it
Regards,
Massimo
>
> On Wed, Oct 3, 2012 at 2:30 PM, M. Manca wrote:
>
>> **
>> Il 03/10/2012 20:14, Jean-Sebastien Stoezel ha scritto:
>>
>>>
>>> Re 10uF capacitor: look up the schematic that comes with AN10974.
>>>
>> I know perfectly that application note, there is no schematic but just a
>> sketch and it shows clearly that 10uF capacitor is a decoupling
>> capacitor on the positive power supply and that there is a 100nF
>> capacitor very near pin 8 of an 8 pin dip i.c. that usually is the
>> VCC/VDD pin.
>> So you are wrong.
>>
>>> This is
>>> how it was designed by NXP to provide measurements on the ADC.
>>> Understood about using active filters. Not practical though when you want
>>> to have a gain <1 and do not necessarily want to run dual rail power
>>> supplies.
>>>
>> I don't see any problem both for gain and for power supply, you
should
>> need a rail to rail operational amplifier, it is a common solution.
>>
>> Please before to say that the ADC is not correctly designed check better
>> your design and your knowledge, you should improve your analogic design
>> capabilities. You should consider to use a good simulation tool as
>> should be LTSpice IV from Linear Technologies (that is free) and start
>> to design some active filter (there are some simple configurations with
>> a 0.707 gain) and band limited amplifiers.
>>
>>>
>>> On Wed, Oct 3, 2012 at 12:30 PM, M. Manca
>>>
>>> >wrote:
>>>> Il 03/10/2012 18:17, Jean-Sebastien Stoezel ha scritto:
>>>>> I have to say I am more and more confused by the way the ADC works
>>> on an
>>>>> LPC1768, and actually how to properly use it.
>>>>>
>>>>> I am aware there has been a lot of discussions about it and I know
>> NXP
>>>> has
>>>>> tried to calm things down by releasing AN10974 but still: it seems
>> the
>>>> ADC
>>>>> is highly susceptible to any type of capacitive load connected to
>>> it. The
>>>>> schematics that come with AN10974 suggest you should be able to
>>> connect
>>>>> 10uF to an analog input.
>>>> No, this is not written, it is written that a 10uF electrolytic
>>>> capacitor (tantalum is better) should be used (better with a series
>>>> inductor) to form a low pass decoupling filter. This means that a low
>>>> pass LC filter should be connected very near the power supply input.
>>>> Then you should place a 100nF ceramic capacitor very near to the analog
>>>> positive power supply pin and connect the other pin to the analog power
>>>> supply ground pin.
>>>> Tried this and the ADC becomes unstable. Tried
>>>>> several capacitor values, as soon as you connect anything higher than
>>>> 100pF
>>>>> spikes start appearing the reading (full scale errors).
>>>> Normally this is a symptom of poor ADC power supply filtering and poor
>>>> knowledge of ADC modules integrated on microcontrollers.
>>>>
>>>> Just to be clear: the error is to think that an 8 input ADC is a
>>>> monolithic block exposing an high impedance on every input.
>>>> This is not correct because the ADC block is made by a single input ADC
>>>> connected to a sample and hold (SH) circuit connected to an analog 8
>>>> channel demultiplexer. The ADC input that is not accessible outside the
>>>> microcontroller has an high impedance value but this is not true for
>> the
>>>> demultiplexer that connects in turn the 8 analog inputs to the SH. So
>>>> considering that SH circutis works well ONLY if the leakage current of
>>>> its input capacitor (that is realized inside the microcontroller) is
>>>> very low, it is not a good idea to connect in parallel with it an
>>>> electrolytic capacitor that has the highest leakage current possible
>>>> (especially if it is an Aluminum type). The leakage current of a 10 uF
>>>> electrolytic capacitor should be in the order of several tenths of uA,
>>>> instead the leakage current of a 100 nF ceramic capacitor is in the
>>>> order of units of nA and for this reason when you connect a ceramic
>>>> capacitor you don't see this problem.
>>>>> This makes me
>>>>> believe that the Cia value of 15pF in the datasheet in table 18 is
>>>> actually
>>>>> the maximum capacitor value that can be connected to an ADC input.
>>>> No, Cia is the capacitance exposed by an analog pin to the external
>>>> circuits; you have to think at it as if there is a 15pF capacitor
>>>> connected just before the analog input pins and the ADC ground pin and
>>>> take care of this designing your interface circuits. 15pF is the sum of
>>>> the SH input capacitor and the input capacitance (in parallel to the SH
>>>> capacitance because the series resistance of the demultiplexer channel
>>>> is near null) of a single analog input of the demultiplexer.
>>>>> Mind you I have been testing this on an MBed, which doesn't
>>> necessarily
>>>>> follow AN10974 layout guidelines. Nonetheless, the ADC conversions
>>> from
>>>> an
>>>>> MBed are very stable if no capacitor is connected to the ADC input.
>>>> Technically speaking the problem is totally due to the electrolytic
>>>> capacitor, your interface circuit (that I don't know) and ADC power
>>>> supply filtering.
>>>>
>>>> I personally verify the LPC17xx ADC operations on Keil MCB1700,
>>>> LpcXpresso-1769, mbed and LPC1788-SK (also some user reported the same
>>>> problem on 1788 parts) to give a more objective results then NXP field
>>>> engineers. The ADC is perfectly operational and connecting filters on
>>>> the inputs its performance is also better. Until now I found problems
>>>> due to poor design of the interface circuit and ADC analog inputs
>>>> programming errors so the ADC performance is heavily influenced by
>>>> engineers skill and expertise to design analog circuits.
>>>>
>>>> In my opinion placing a 10uF electrolytic Aluminum capacitor directly
>> in
>>>> parallel to an analog input pit is a poor design practice.
>>>>
>>>> The correct way to design an ADC interface circuit is to design an
>>>> amplifier circuit (with a gain > 1 if needed) to interface and
>>>> decoupling the input sensor to the ADC input possibly using an
>>>> operational amplifier considering that it has a very low impedance
>>>> output circuit. The amplifier circuit should also integrate an anti
>>>> alias filtering capabilities and should be tailored specifically for
>> the
>>>> ADC conversion rate (lower then 1/2 of the conversion rate).
>>>>> Jean
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> On Tue, Oct 2, 2012 at 9:58 PM, misterhershel
>>> >
>>>> wrote:
>>>>>> **
>>>>>>
>>>>>>
>>>>>> The sampling capacitor internal to the ADC is connected to the
>> input,
>>>>>> prior to a conversion. The state of charge on this capacitor, is
>>>>>> transferred to the input circuitry.
>>>>>>
>>>>>> This can be a problem if the source impedance is high, because the
>>>>>> conversion can start, before the source has a chance to charge
>>> the cap.
>>>>>> This is also a problem when sampling multiple channels, because the
>>>>>> resulting charge on the cap from one channel, is transferred to the
>>>> source
>>>>>> for the next channel.
>>>>>>
>>>>>> To make matters worse, there is no way to increase the delay between
>>>>>> channel switching and start of conversion (other then slowing the
>>>>>> conversion rate).
>>>>>>
>>>>>> For whatever reason, NXP has, as far as I can see, just about zero
>>>>>> information on this subject.
>>>>>>
>>>>>> The MSP430 internal ADCs are similar, and explained in detail in the
>>>> Texas
>>>>>> Instrument docs.
>>>>>>
>>>>>> -Hershel
>>>>>>
>>>>>>
>>>>>> --- In l...
>>> , Olivier Gautherot
>> wrote:
>>>>>>> Jean-Sastien,
>>>>>>>
>>>>>>> there is no theoretical limit for the capacitor connected to the
>>> input
>>>>>> and
>>>>>>> I would even recommend to put one if the signal you want to measure
>>>> has a
>>>>>>> high impedance (from the top of my head, NXP recommends an
>>> impedance of
>>>>>> 2K
>>>>>>> max or something like that). We built a test board in the office
>>> which
>>>>>> has
>>>>>>> a temperature sensor on ADC0 and the first tests reported
>>> measurements
>>>>>> that
>>>>>>> were clearly out of range. I eventually figured out that a second
>>>> reading
>>>>>>> would give the right value.
>>>>>>>
>>>>>>> We finally discovered that the temperature sensor had an output
>>> current
>>>>>> of
>>>>>>> 10uA max and had to be "buffered" with a small cap (0.1uF was
>>>> sufficient
>>>>>> in
>>>>>>> this case). It seems that the internal analog switch has an
>>> effect on
>>>> the
>>>>>>> input pin impedance.
>>>>>>>
>>>>>>> Hope it helps
>>>>>>> --
>>>>>>> Olivier Gautherot
>>>>>>> olivier@...
>>>>>>> www.gautherot.net
>>>>>>> http://www.linkedin.com/in/ogautherot
>>>>>>>
>>>>>>> On Wed, Sep 26, 2012 at 6:43 PM, k_erkens wrote:
>>>>>>>
>>>>>>>> **
>>>>>>>>
>>>>>>>>
>>>>>>>> If im not mistaken, the value in the datasheet represents the
>>> internal
>>>>>>>> capacitance of the chip.
>>>>>>>> Because its an input you can probably put any value you want at
>> the
>>>>>> input.
>>>>>>>> --
>>>>>>>> Kevin
>>>>>>>>
>>>>>>>> --- In l...
>>> , Jean-Sebastien Stoezel
>>>>>>>> wrote:
>>>>>>>>> Hi:
>>>>>>>>>
>>>>>>>>> Looking at the datasheet of the LPC1768, it seems table 18 lists
>>>>>> 15pF Cia
>>>>>>>>> as the maximum input capacitance that can be connected to an
>>> analog
>>>>>>>> input.
>>>>>>>>> This seems rather small and limiting.
>>>>>>>>> Looking at the board designed specifically for AN10974, the
>>> schematic
>>>>>>>> shows
>>>>>>>>> capacitors of 10uF and 0.1uF connected to the analog inputs...
>>>>>>>>>
>>>>>>>>> What is the actual maximum capacitance value that can be
>> connected
>>>>>> to the
>>>>>>>>> input of an analog input, on an LPC1768?
>>>>>>>>>
>>>>>>>>> Thanks,
>>>>>>>>> Jean
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
Clarifications on maximum input capacitance on input of ADC on LPC1768
Started by ●September 26, 2012
Reply by ●October 3, 20122012-10-03
Reply by ●October 3, 20122012-10-03
This is the direct link to all files used for AN10974, including schematics
for the test board
http://www.nxp.com/documents/application_note/AN10974_-_LPC176x_175x_12-bit_ADC_design_guidelines.zip
On Wed, Oct 3, 2012 at 3:20 PM, M. Manca wrote:
> Il 03/10/2012 21:35, Jean-Sebastien Stoezel ha scritto:
> > Schematic attached, check page 2.
> There is no schematic attached. You can send me it directly at
> m...@micronengineering.it
> Regards,
> Massimo
> >
> >
> >
> > On Wed, Oct 3, 2012 at 2:30 PM, M. Manca > >wrote:
> >
> >> **
> >>
> >>
> >> Il 03/10/2012 20:14, Jean-Sebastien Stoezel ha scritto:
> >>
> >>>
> >>> Re 10uF capacitor: look up the schematic that comes with AN10974.
> >>>
> >> I know perfectly that application note, there is no schematic but just a
> >> sketch and it shows clearly that 10uF capacitor is a decoupling
> >> capacitor on the positive power supply and that there is a 100nF
> >> capacitor very near pin 8 of an 8 pin dip i.c. that usually is the
> >> VCC/VDD pin.
> >> So you are wrong.
> >>
> >>> This is
> >>> how it was designed by NXP to provide measurements on the ADC.
> >>> Understood about using active filters. Not practical though when you
> want
> >>> to have a gain <1 and do not necessarily want to run dual rail power
> >>> supplies.
> >>>
> >> I don't see any problem both for gain and for power supply, you should
> >> need a rail to rail operational amplifier, it is a common solution.
> >>
> >> Please before to say that the ADC is not correctly designed check better
> >> your design and your knowledge, you should improve your analogic design
> >> capabilities. You should consider to use a good simulation tool as
> >> should be LTSpice IV from Linear Technologies (that is free) and start
> >> to design some active filter (there are some simple configurations with
> >> a 0.707 gain) and band limited amplifiers.
> >>
> >>>
> >>> On Wed, Oct 3, 2012 at 12:30 PM, M. Manca
> >>> > >>> >wrote:
> >>>> Il 03/10/2012 18:17, Jean-Sebastien Stoezel ha scritto:
> >>>>> I have to say I am more and more confused by the way the ADC works
> >>> on an
> >>>>> LPC1768, and actually how to properly use it.
> >>>>>
> >>>>> I am aware there has been a lot of discussions about it and I know
> >> NXP
> >>>> has
> >>>>> tried to calm things down by releasing AN10974 but still: it seems
> >> the
> >>>> ADC
> >>>>> is highly susceptible to any type of capacitive load connected to
> >>> it. The
> >>>>> schematics that come with AN10974 suggest you should be able to
> >>> connect
> >>>>> 10uF to an analog input.
> >>>> No, this is not written, it is written that a 10uF electrolytic
> >>>> capacitor (tantalum is better) should be used (better with a series
> >>>> inductor) to form a low pass decoupling filter. This means that a low
> >>>> pass LC filter should be connected very near the power supply input.
> >>>> Then you should place a 100nF ceramic capacitor very near to the
> analog
> >>>> positive power supply pin and connect the other pin to the analog
> power
> >>>> supply ground pin.
> >>>> Tried this and the ADC becomes unstable. Tried
> >>>>> several capacitor values, as soon as you connect anything higher than
> >>>> 100pF
> >>>>> spikes start appearing the reading (full scale errors).
> >>>> Normally this is a symptom of poor ADC power supply filtering and poor
> >>>> knowledge of ADC modules integrated on microcontrollers.
> >>>>
> >>>> Just to be clear: the error is to think that an 8 input ADC is a
> >>>> monolithic block exposing an high impedance on every input.
> >>>> This is not correct because the ADC block is made by a single input
> ADC
> >>>> connected to a sample and hold (SH) circuit connected to an analog 8
> >>>> channel demultiplexer. The ADC input that is not accessible outside
> the
> >>>> microcontroller has an high impedance value but this is not true for
> >> the
> >>>> demultiplexer that connects in turn the 8 analog inputs to the SH. So
> >>>> considering that SH circutis works well ONLY if the leakage current of
> >>>> its input capacitor (that is realized inside the microcontroller) is
> >>>> very low, it is not a good idea to connect in parallel with it an
> >>>> electrolytic capacitor that has the highest leakage current possible
> >>>> (especially if it is an Aluminum type). The leakage current of a 10 uF
> >>>> electrolytic capacitor should be in the order of several tenths of uA,
> >>>> instead the leakage current of a 100 nF ceramic capacitor is in the
> >>>> order of units of nA and for this reason when you connect a ceramic
> >>>> capacitor you don't see this problem.
> >>>>> This makes me
> >>>>> believe that the Cia value of 15pF in the datasheet in table 18 is
> >>>> actually
> >>>>> the maximum capacitor value that can be connected to an ADC input.
> >>>> No, Cia is the capacitance exposed by an analog pin to the external
> >>>> circuits; you have to think at it as if there is a 15pF capacitor
> >>>> connected just before the analog input pins and the ADC ground pin and
> >>>> take care of this designing your interface circuits. 15pF is the sum
> of
> >>>> the SH input capacitor and the input capacitance (in parallel to the
> SH
> >>>> capacitance because the series resistance of the demultiplexer channel
> >>>> is near null) of a single analog input of the demultiplexer.
> >>>>> Mind you I have been testing this on an MBed, which doesn't
> >>> necessarily
> >>>>> follow AN10974 layout guidelines. Nonetheless, the ADC conversions
> >>> from
> >>>> an
> >>>>> MBed are very stable if no capacitor is connected to the ADC input.
> >>>> Technically speaking the problem is totally due to the electrolytic
> >>>> capacitor, your interface circuit (that I don't know) and ADC power
> >>>> supply filtering.
> >>>>
> >>>> I personally verify the LPC17xx ADC operations on Keil MCB1700,
> >>>> LpcXpresso-1769, mbed and LPC1788-SK (also some user reported the same
> >>>> problem on 1788 parts) to give a more objective results then NXP field
> >>>> engineers. The ADC is perfectly operational and connecting filters on
> >>>> the inputs its performance is also better. Until now I found problems
> >>>> due to poor design of the interface circuit and ADC analog inputs
> >>>> programming errors so the ADC performance is heavily influenced by
> >>>> engineers skill and expertise to design analog circuits.
> >>>>
> >>>> In my opinion placing a 10uF electrolytic Aluminum capacitor directly
> >> in
> >>>> parallel to an analog input pit is a poor design practice.
> >>>>
> >>>> The correct way to design an ADC interface circuit is to design an
> >>>> amplifier circuit (with a gain > 1 if needed) to interface and
> >>>> decoupling the input sensor to the ADC input possibly using an
> >>>> operational amplifier considering that it has a very low impedance
> >>>> output circuit. The amplifier circuit should also integrate an anti
> >>>> alias filtering capabilities and should be tailored specifically for
> >> the
> >>>> ADC conversion rate (lower then 1/2 of the conversion rate).
> >>>>> Jean
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>> On Tue, Oct 2, 2012 at 9:58 PM, misterhershel
> >>> >
> >>>> wrote:
> >>>>>> **
> >>>>>>
> >>>>>>
> >>>>>> The sampling capacitor internal to the ADC is connected to the
> >> input,
> >>>>>> prior to a conversion. The state of charge on this capacitor, is
> >>>>>> transferred to the input circuitry.
> >>>>>>
> >>>>>> This can be a problem if the source impedance is high, because the
> >>>>>> conversion can start, before the source has a chance to charge
> >>> the cap.
> >>>>>> This is also a problem when sampling multiple channels, because the
> >>>>>> resulting charge on the cap from one channel, is transferred to the
> >>>> source
> >>>>>> for the next channel.
> >>>>>>
> >>>>>> To make matters worse, there is no way to increase the delay between
> >>>>>> channel switching and start of conversion (other then slowing the
> >>>>>> conversion rate).
> >>>>>>
> >>>>>> For whatever reason, NXP has, as far as I can see, just about zero
> >>>>>> information on this subject.
> >>>>>>
> >>>>>> The MSP430 internal ADCs are similar, and explained in detail in the
> >>>> Texas
> >>>>>> Instrument docs.
> >>>>>>
> >>>>>> -Hershel
> >>>>>>
> >>>>>>
> >>>>>> --- In l...
> >>> , Olivier Gautherot
> >> wrote:
> >>>>>>> Jean-Sastien,
> >>>>>>>
> >>>>>>> there is no theoretical limit for the capacitor connected to the
> >>> input
> >>>>>> and
> >>>>>>> I would even recommend to put one if the signal you want to measure
> >>>> has a
> >>>>>>> high impedance (from the top of my head, NXP recommends an
> >>> impedance of
> >>>>>> 2K
> >>>>>>> max or something like that). We built a test board in the office
> >>> which
> >>>>>> has
> >>>>>>> a temperature sensor on ADC0 and the first tests reported
> >>> measurements
> >>>>>> that
> >>>>>>> were clearly out of range. I eventually figured out that a second
> >>>> reading
> >>>>>>> would give the right value.
> >>>>>>>
> >>>>>>> We finally discovered that the temperature sensor had an output
> >>> current
> >>>>>> of
> >>>>>>> 10uA max and had to be "buffered" with a small cap (0.1uF was
> >>>> sufficient
> >>>>>> in
> >>>>>>> this case). It seems that the internal analog switch has an
> >>> effect on
> >>>> the
> >>>>>>> input pin impedance.
> >>>>>>>
> >>>>>>> Hope it helps
> >>>>>>> --
> >>>>>>> Olivier Gautherot
> >>>>>>> olivier@...
> >>>>>>> www.gautherot.net
> >>>>>>> http://www.linkedin.com/in/ogautherot
> >>>>>>>
> >>>>>>> On Wed, Sep 26, 2012 at 6:43 PM, k_erkens wrote:
> >>>>>>>
> >>>>>>>> **
> >>>>>>>>
> >>>>>>>>
> >>>>>>>> If im not mistaken, the value in the datasheet represents the
> >>> internal
> >>>>>>>> capacitance of the chip.
> >>>>>>>> Because its an input you can probably put any value you want at
> >> the
> >>>>>> input.
> >>>>>>>> --
> >>>>>>>> Kevin
> >>>>>>>>
> >>>>>>>> --- In l...
> >>> , Jean-Sebastien Stoezel
>
> >>>>>>>> wrote:
> >>>>>>>>> Hi:
> >>>>>>>>>
> >>>>>>>>> Looking at the datasheet of the LPC1768, it seems table 18 lists
> >>>>>> 15pF Cia
> >>>>>>>>> as the maximum input capacitance that can be connected to an
> >>> analog
> >>>>>>>> input.
> >>>>>>>>> This seems rather small and limiting.
> >>>>>>>>> Looking at the board designed specifically for AN10974, the
> >>> schematic
> >>>>>>>> shows
> >>>>>>>>> capacitors of 10uF and 0.1uF connected to the analog inputs...
> >>>>>>>>>
> >>>>>>>>> What is the actual maximum capacitance value that can be
> >> connected
> >>>>>> to the
> >>>>>>>>> input of an analog input, on an LPC1768?
> >>>>>>>>>
> >>>>>>>>> Thanks,
> >>>>>>>>> Jean
> >>>>>>>>>
> >>>>>>>>>
> >>>>>>>>>
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
for the test board
http://www.nxp.com/documents/application_note/AN10974_-_LPC176x_175x_12-bit_ADC_design_guidelines.zip
On Wed, Oct 3, 2012 at 3:20 PM, M. Manca wrote:
> Il 03/10/2012 21:35, Jean-Sebastien Stoezel ha scritto:
> > Schematic attached, check page 2.
> There is no schematic attached. You can send me it directly at
> m...@micronengineering.it
> Regards,
> Massimo
> >
> >
> >
> > On Wed, Oct 3, 2012 at 2:30 PM, M. Manca > >wrote:
> >
> >> **
> >>
> >>
> >> Il 03/10/2012 20:14, Jean-Sebastien Stoezel ha scritto:
> >>
> >>>
> >>> Re 10uF capacitor: look up the schematic that comes with AN10974.
> >>>
> >> I know perfectly that application note, there is no schematic but just a
> >> sketch and it shows clearly that 10uF capacitor is a decoupling
> >> capacitor on the positive power supply and that there is a 100nF
> >> capacitor very near pin 8 of an 8 pin dip i.c. that usually is the
> >> VCC/VDD pin.
> >> So you are wrong.
> >>
> >>> This is
> >>> how it was designed by NXP to provide measurements on the ADC.
> >>> Understood about using active filters. Not practical though when you
> want
> >>> to have a gain <1 and do not necessarily want to run dual rail power
> >>> supplies.
> >>>
> >> I don't see any problem both for gain and for power supply, you should
> >> need a rail to rail operational amplifier, it is a common solution.
> >>
> >> Please before to say that the ADC is not correctly designed check better
> >> your design and your knowledge, you should improve your analogic design
> >> capabilities. You should consider to use a good simulation tool as
> >> should be LTSpice IV from Linear Technologies (that is free) and start
> >> to design some active filter (there are some simple configurations with
> >> a 0.707 gain) and band limited amplifiers.
> >>
> >>>
> >>> On Wed, Oct 3, 2012 at 12:30 PM, M. Manca
> >>> > >>> >wrote:
> >>>> Il 03/10/2012 18:17, Jean-Sebastien Stoezel ha scritto:
> >>>>> I have to say I am more and more confused by the way the ADC works
> >>> on an
> >>>>> LPC1768, and actually how to properly use it.
> >>>>>
> >>>>> I am aware there has been a lot of discussions about it and I know
> >> NXP
> >>>> has
> >>>>> tried to calm things down by releasing AN10974 but still: it seems
> >> the
> >>>> ADC
> >>>>> is highly susceptible to any type of capacitive load connected to
> >>> it. The
> >>>>> schematics that come with AN10974 suggest you should be able to
> >>> connect
> >>>>> 10uF to an analog input.
> >>>> No, this is not written, it is written that a 10uF electrolytic
> >>>> capacitor (tantalum is better) should be used (better with a series
> >>>> inductor) to form a low pass decoupling filter. This means that a low
> >>>> pass LC filter should be connected very near the power supply input.
> >>>> Then you should place a 100nF ceramic capacitor very near to the
> analog
> >>>> positive power supply pin and connect the other pin to the analog
> power
> >>>> supply ground pin.
> >>>> Tried this and the ADC becomes unstable. Tried
> >>>>> several capacitor values, as soon as you connect anything higher than
> >>>> 100pF
> >>>>> spikes start appearing the reading (full scale errors).
> >>>> Normally this is a symptom of poor ADC power supply filtering and poor
> >>>> knowledge of ADC modules integrated on microcontrollers.
> >>>>
> >>>> Just to be clear: the error is to think that an 8 input ADC is a
> >>>> monolithic block exposing an high impedance on every input.
> >>>> This is not correct because the ADC block is made by a single input
> ADC
> >>>> connected to a sample and hold (SH) circuit connected to an analog 8
> >>>> channel demultiplexer. The ADC input that is not accessible outside
> the
> >>>> microcontroller has an high impedance value but this is not true for
> >> the
> >>>> demultiplexer that connects in turn the 8 analog inputs to the SH. So
> >>>> considering that SH circutis works well ONLY if the leakage current of
> >>>> its input capacitor (that is realized inside the microcontroller) is
> >>>> very low, it is not a good idea to connect in parallel with it an
> >>>> electrolytic capacitor that has the highest leakage current possible
> >>>> (especially if it is an Aluminum type). The leakage current of a 10 uF
> >>>> electrolytic capacitor should be in the order of several tenths of uA,
> >>>> instead the leakage current of a 100 nF ceramic capacitor is in the
> >>>> order of units of nA and for this reason when you connect a ceramic
> >>>> capacitor you don't see this problem.
> >>>>> This makes me
> >>>>> believe that the Cia value of 15pF in the datasheet in table 18 is
> >>>> actually
> >>>>> the maximum capacitor value that can be connected to an ADC input.
> >>>> No, Cia is the capacitance exposed by an analog pin to the external
> >>>> circuits; you have to think at it as if there is a 15pF capacitor
> >>>> connected just before the analog input pins and the ADC ground pin and
> >>>> take care of this designing your interface circuits. 15pF is the sum
> of
> >>>> the SH input capacitor and the input capacitance (in parallel to the
> SH
> >>>> capacitance because the series resistance of the demultiplexer channel
> >>>> is near null) of a single analog input of the demultiplexer.
> >>>>> Mind you I have been testing this on an MBed, which doesn't
> >>> necessarily
> >>>>> follow AN10974 layout guidelines. Nonetheless, the ADC conversions
> >>> from
> >>>> an
> >>>>> MBed are very stable if no capacitor is connected to the ADC input.
> >>>> Technically speaking the problem is totally due to the electrolytic
> >>>> capacitor, your interface circuit (that I don't know) and ADC power
> >>>> supply filtering.
> >>>>
> >>>> I personally verify the LPC17xx ADC operations on Keil MCB1700,
> >>>> LpcXpresso-1769, mbed and LPC1788-SK (also some user reported the same
> >>>> problem on 1788 parts) to give a more objective results then NXP field
> >>>> engineers. The ADC is perfectly operational and connecting filters on
> >>>> the inputs its performance is also better. Until now I found problems
> >>>> due to poor design of the interface circuit and ADC analog inputs
> >>>> programming errors so the ADC performance is heavily influenced by
> >>>> engineers skill and expertise to design analog circuits.
> >>>>
> >>>> In my opinion placing a 10uF electrolytic Aluminum capacitor directly
> >> in
> >>>> parallel to an analog input pit is a poor design practice.
> >>>>
> >>>> The correct way to design an ADC interface circuit is to design an
> >>>> amplifier circuit (with a gain > 1 if needed) to interface and
> >>>> decoupling the input sensor to the ADC input possibly using an
> >>>> operational amplifier considering that it has a very low impedance
> >>>> output circuit. The amplifier circuit should also integrate an anti
> >>>> alias filtering capabilities and should be tailored specifically for
> >> the
> >>>> ADC conversion rate (lower then 1/2 of the conversion rate).
> >>>>> Jean
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>> On Tue, Oct 2, 2012 at 9:58 PM, misterhershel
> >>> >
> >>>> wrote:
> >>>>>> **
> >>>>>>
> >>>>>>
> >>>>>> The sampling capacitor internal to the ADC is connected to the
> >> input,
> >>>>>> prior to a conversion. The state of charge on this capacitor, is
> >>>>>> transferred to the input circuitry.
> >>>>>>
> >>>>>> This can be a problem if the source impedance is high, because the
> >>>>>> conversion can start, before the source has a chance to charge
> >>> the cap.
> >>>>>> This is also a problem when sampling multiple channels, because the
> >>>>>> resulting charge on the cap from one channel, is transferred to the
> >>>> source
> >>>>>> for the next channel.
> >>>>>>
> >>>>>> To make matters worse, there is no way to increase the delay between
> >>>>>> channel switching and start of conversion (other then slowing the
> >>>>>> conversion rate).
> >>>>>>
> >>>>>> For whatever reason, NXP has, as far as I can see, just about zero
> >>>>>> information on this subject.
> >>>>>>
> >>>>>> The MSP430 internal ADCs are similar, and explained in detail in the
> >>>> Texas
> >>>>>> Instrument docs.
> >>>>>>
> >>>>>> -Hershel
> >>>>>>
> >>>>>>
> >>>>>> --- In l...
> >>> , Olivier Gautherot
> >> wrote:
> >>>>>>> Jean-Sastien,
> >>>>>>>
> >>>>>>> there is no theoretical limit for the capacitor connected to the
> >>> input
> >>>>>> and
> >>>>>>> I would even recommend to put one if the signal you want to measure
> >>>> has a
> >>>>>>> high impedance (from the top of my head, NXP recommends an
> >>> impedance of
> >>>>>> 2K
> >>>>>>> max or something like that). We built a test board in the office
> >>> which
> >>>>>> has
> >>>>>>> a temperature sensor on ADC0 and the first tests reported
> >>> measurements
> >>>>>> that
> >>>>>>> were clearly out of range. I eventually figured out that a second
> >>>> reading
> >>>>>>> would give the right value.
> >>>>>>>
> >>>>>>> We finally discovered that the temperature sensor had an output
> >>> current
> >>>>>> of
> >>>>>>> 10uA max and had to be "buffered" with a small cap (0.1uF was
> >>>> sufficient
> >>>>>> in
> >>>>>>> this case). It seems that the internal analog switch has an
> >>> effect on
> >>>> the
> >>>>>>> input pin impedance.
> >>>>>>>
> >>>>>>> Hope it helps
> >>>>>>> --
> >>>>>>> Olivier Gautherot
> >>>>>>> olivier@...
> >>>>>>> www.gautherot.net
> >>>>>>> http://www.linkedin.com/in/ogautherot
> >>>>>>>
> >>>>>>> On Wed, Sep 26, 2012 at 6:43 PM, k_erkens wrote:
> >>>>>>>
> >>>>>>>> **
> >>>>>>>>
> >>>>>>>>
> >>>>>>>> If im not mistaken, the value in the datasheet represents the
> >>> internal
> >>>>>>>> capacitance of the chip.
> >>>>>>>> Because its an input you can probably put any value you want at
> >> the
> >>>>>> input.
> >>>>>>>> --
> >>>>>>>> Kevin
> >>>>>>>>
> >>>>>>>> --- In l...
> >>> , Jean-Sebastien Stoezel
>
> >>>>>>>> wrote:
> >>>>>>>>> Hi:
> >>>>>>>>>
> >>>>>>>>> Looking at the datasheet of the LPC1768, it seems table 18 lists
> >>>>>> 15pF Cia
> >>>>>>>>> as the maximum input capacitance that can be connected to an
> >>> analog
> >>>>>>>> input.
> >>>>>>>>> This seems rather small and limiting.
> >>>>>>>>> Looking at the board designed specifically for AN10974, the
> >>> schematic
> >>>>>>>> shows
> >>>>>>>>> capacitors of 10uF and 0.1uF connected to the analog inputs...
> >>>>>>>>>
> >>>>>>>>> What is the actual maximum capacitance value that can be
> >> connected
> >>>>>> to the
> >>>>>>>>> input of an analog input, on an LPC1768?
> >>>>>>>>>
> >>>>>>>>> Thanks,
> >>>>>>>>> Jean
> >>>>>>>>>
> >>>>>>>>>
> >>>>>>>>>
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
Reply by ●October 4, 20122012-10-04
Hi Jean-Sebastian,
M.Manca is right that the best way for a successful result is to put an opamp buffer on the ADC input. You do not need dual rail supplies, there are plenty of opamps that will run off the 3.3V supply for the processor.
The NXP schematic does show a 10uF cap on each input but in my experience, NXP data sheets are full of mistakes and examples that do not work in the real world.
How long a delay do you have in your software between switching the ADC input multiplexer and starting the conversion? If you select the input then immediately start the conversion this can cause all sorts of odd results.
--
Tim Mitchell
M.Manca is right that the best way for a successful result is to put an opamp buffer on the ADC input. You do not need dual rail supplies, there are plenty of opamps that will run off the 3.3V supply for the processor.
The NXP schematic does show a 10uF cap on each input but in my experience, NXP data sheets are full of mistakes and examples that do not work in the real world.
How long a delay do you have in your software between switching the ADC input multiplexer and starting the conversion? If you select the input then immediately start the conversion this can cause all sorts of odd results.
--
Tim Mitchell
Reply by ●October 4, 20122012-10-04
Il 04/10/2012 11:10, Tim Mitchell ha scritto:
>
>
> Hi Jean-Sebastian,
>
> M.Manca is right that the best way for a successful result is to put
> an opamp buffer on the ADC input. You do not need dual rail supplies,
> there are plenty of opamps that will run off the 3.3V supply for the
> processor.
>
> The NXP schematic does show a 10uF cap on each input but in my
> experience, NXP data sheets are full of mistakes and examples that do
> not work in the real world.
>
In this case there is something strange also in the release of the
application note because I have stored in my server only the pdf with a
file date well before the file you can find in nxp.com and lpcware.com
both having also the zip file that I haven't in the archive. It is quite
strange.
> How long a delay do you have in your software between switching the
> ADC input multiplexer and starting the conversion? If you select the
> input then immediately start the conversion this can cause all sorts
> of odd results.
>
> --
> Tim Mitchell
>
>
> Hi Jean-Sebastian,
>
> M.Manca is right that the best way for a successful result is to put
> an opamp buffer on the ADC input. You do not need dual rail supplies,
> there are plenty of opamps that will run off the 3.3V supply for the
> processor.
>
> The NXP schematic does show a 10uF cap on each input but in my
> experience, NXP data sheets are full of mistakes and examples that do
> not work in the real world.
>
In this case there is something strange also in the release of the
application note because I have stored in my server only the pdf with a
file date well before the file you can find in nxp.com and lpcware.com
both having also the zip file that I haven't in the archive. It is quite
strange.
> How long a delay do you have in your software between switching the
> ADC input multiplexer and starting the conversion? If you select the
> input then immediately start the conversion this can cause all sorts
> of odd results.
>
> --
> Tim Mitchell
Reply by ●October 4, 20122012-10-04
Hi Tim:
Thanks for the reply.
> You do not need dual rail supplies, there are plenty of opamps that will run off the 3.3V supply for the processor.
>
This is understood. Like most applications the voltages i am measuring are greater than 3.3V and need to be stepped down.
Like I said in a previous post what I recall from opamp courses is that if you want a gain <1 you will have to use an inverter circuit which requires dual rails. I guess you are suggesting to use a follower just to provide impedance adaptation. There would be a first stage with a voltage divider associated capacitor to for an RC. This would feed into a follower that would isolate the ADC from the capacitor.
In the first prototype I built I was we'll aware of the ADC difficulties to cope with capacitive loads. I opted for an active RC filter which also adapted the voltage input. I used an inverter scheme and had to use dual rails.
> How long a delay do you have in your software between switching the ADC input multiplexer and starting the conversion? If you select the input then immediately start the conversion this can cause all sorts of odd results.
>
I use the ADC in burst mode and collect samples on the fly and do not control the multiplexer switching.
Lately I have been using an MBed to test analog interfaces. I have to say I have been using the AnalogIn interface. I am not sure how delays are handled in this library.
Jean-Sebastien
On 2012-10-04, at 4:10 AM, "Tim Mitchell" wrote:
> Hi Jean-Sebastian,
>
> M.Manca is right that the best way for a successful result is to put an opamp buffer on the ADC input. You do not need dual rail supplies, there are plenty of opamps that will run off the 3.3V supply for the processor.
>
> The NXP schematic does show a 10uF cap on each input but in my experience, NXP data sheets are full of mistakes and examples that do not work in the real world.
>
> How long a delay do you have in your software between switching the ADC input multiplexer and starting the conversion? If you select the input then immediately start the conversion this can cause all sorts of odd results.
>
> --
> Tim Mitchell
Thanks for the reply.
> You do not need dual rail supplies, there are plenty of opamps that will run off the 3.3V supply for the processor.
>
This is understood. Like most applications the voltages i am measuring are greater than 3.3V and need to be stepped down.
Like I said in a previous post what I recall from opamp courses is that if you want a gain <1 you will have to use an inverter circuit which requires dual rails. I guess you are suggesting to use a follower just to provide impedance adaptation. There would be a first stage with a voltage divider associated capacitor to for an RC. This would feed into a follower that would isolate the ADC from the capacitor.
In the first prototype I built I was we'll aware of the ADC difficulties to cope with capacitive loads. I opted for an active RC filter which also adapted the voltage input. I used an inverter scheme and had to use dual rails.
> How long a delay do you have in your software between switching the ADC input multiplexer and starting the conversion? If you select the input then immediately start the conversion this can cause all sorts of odd results.
>
I use the ADC in burst mode and collect samples on the fly and do not control the multiplexer switching.
Lately I have been using an MBed to test analog interfaces. I have to say I have been using the AnalogIn interface. I am not sure how delays are handled in this library.
Jean-Sebastien
On 2012-10-04, at 4:10 AM, "Tim Mitchell" wrote:
> Hi Jean-Sebastian,
>
> M.Manca is right that the best way for a successful result is to put an opamp buffer on the ADC input. You do not need dual rail supplies, there are plenty of opamps that will run off the 3.3V supply for the processor.
>
> The NXP schematic does show a 10uF cap on each input but in my experience, NXP data sheets are full of mistakes and examples that do not work in the real world.
>
> How long a delay do you have in your software between switching the ADC input multiplexer and starting the conversion? If you select the input then immediately start the conversion this can cause all sorts of odd results.
>
> --
> Tim Mitchell
Reply by ●October 4, 20122012-10-04
For a higher voltage than 3.3V I would use a resistive divider and a unity gain
opamp - assuming your source can drive the resistive divider.
Interesting point about using ADC in burst mode, I do not know if any settling time is allowed - the data sheet does not mention it. I just know I have seen a lot of inaccuracy if I try to change input then immediately start the ADC.
--
Tim Mitchell
Interesting point about using ADC in burst mode, I do not know if any settling time is allowed - the data sheet does not mention it. I just know I have seen a lot of inaccuracy if I try to change input then immediately start the ADC.
--
Tim Mitchell
Reply by ●October 4, 20122012-10-04
Il 04/10/2012 15:42, Tim Mitchell ha scritto:
>
>
> For a higher voltage than 3.3V I would use a resistive divider and a
> unity gain opamp - assuming your source can drive the resistive divider.
>
> Interesting point about using ADC in burst mode, I do not know if any
> settling time is allowed - the data sheet does not mention it. I just
> know I have seen a lot of inaccuracy if I try to change input then
> immediately start the ADC.
>
This is one of the first problem to solve to design an ADC system. The
test to understand if the problem is introduced by the microcontroller
ADC is not so complicate. Supposing that we have an 8 channel ADC we
have to put very different fixed voltages on consecutive pins so that
after a lot of burst cycles and data collection we can see if every
channel data is well read and results are distributed with a variance
compatible with that of a single channel read in single channel mode.
I don't know exactly the internal schematic of the ADC but for SAR ADC
is normal to have a sample and hold circuit between the demultiplexer
and the ADC input so when switching from 2 consecutive channels I know 2
different implementations:
1. the simplest: the SH has 2 switches one before the input capacitor
and the 2nd just after so when changing the channel the 2nd switch is
opened and the 1st closed; in this way the input capacitor will be
charged or discharged (depends by the voltage difference between the
input capacitor and the demultiplexer output pin) and after some time
the 1st switch will be opened and the 2nd will be closed then the ADC
will read the voltage across the input capacitor. This circuit is not so
good because the SH input capacitor should be charged or discharged so
we need to know the turn on and off time of the switches to verify that
our interfaced circuit could work properly.
2. The best: there is a 3th switch in parallel to the SH input capacitor
used to totally discharge the input capacitor before to change the input
channel so the input capacitor will be always charged by our interface
circuit.
I don't know if there are more implementations of ADCs but anyway with
these we can think that if our interface circuit is not able to quickly
charge the SH input capacitor at the same voltage of the analog input
(that is the output of the interface circuit) we will read wrong values.
Knowing SH switch time (settling time of the ADC) should help to
calculate and design better analog interface circuits.
In my designs using LPC17xx ADCs I normally design an anti alias filter
limiting the input bandwidth to 10-20 kHz because until now I read low
speed sensors but should be interesting to experiment a little bit more
with the ADC and anti alias filter for a bandwidth of 100-200kHz and see
the results.
> --
> Tim Mitchell
>
>
> For a higher voltage than 3.3V I would use a resistive divider and a
> unity gain opamp - assuming your source can drive the resistive divider.
>
> Interesting point about using ADC in burst mode, I do not know if any
> settling time is allowed - the data sheet does not mention it. I just
> know I have seen a lot of inaccuracy if I try to change input then
> immediately start the ADC.
>
This is one of the first problem to solve to design an ADC system. The
test to understand if the problem is introduced by the microcontroller
ADC is not so complicate. Supposing that we have an 8 channel ADC we
have to put very different fixed voltages on consecutive pins so that
after a lot of burst cycles and data collection we can see if every
channel data is well read and results are distributed with a variance
compatible with that of a single channel read in single channel mode.
I don't know exactly the internal schematic of the ADC but for SAR ADC
is normal to have a sample and hold circuit between the demultiplexer
and the ADC input so when switching from 2 consecutive channels I know 2
different implementations:
1. the simplest: the SH has 2 switches one before the input capacitor
and the 2nd just after so when changing the channel the 2nd switch is
opened and the 1st closed; in this way the input capacitor will be
charged or discharged (depends by the voltage difference between the
input capacitor and the demultiplexer output pin) and after some time
the 1st switch will be opened and the 2nd will be closed then the ADC
will read the voltage across the input capacitor. This circuit is not so
good because the SH input capacitor should be charged or discharged so
we need to know the turn on and off time of the switches to verify that
our interfaced circuit could work properly.
2. The best: there is a 3th switch in parallel to the SH input capacitor
used to totally discharge the input capacitor before to change the input
channel so the input capacitor will be always charged by our interface
circuit.
I don't know if there are more implementations of ADCs but anyway with
these we can think that if our interface circuit is not able to quickly
charge the SH input capacitor at the same voltage of the analog input
(that is the output of the interface circuit) we will read wrong values.
Knowing SH switch time (settling time of the ADC) should help to
calculate and design better analog interface circuits.
In my designs using LPC17xx ADCs I normally design an anti alias filter
limiting the input bandwidth to 10-20 kHz because until now I read low
speed sensors but should be interesting to experiment a little bit more
with the ADC and anti alias filter for a bandwidth of 100-200kHz and see
the results.
> --
> Tim Mitchell
Reply by ●October 4, 20122012-10-04
Hi Tim:
Thanks for the reply. Looks like we're on the same page for the analog
interface.
As for the software side, do you have an example you could share to
illustrate your recommendations to add delays when setting up the ADC?
Thanks,
JS
On Thu, Oct 4, 2012 at 8:42 AM, Tim Mitchell wrote:
> **
> For a higher voltage than 3.3V I would use a resistive divider and a unity
> gain opamp - assuming your source can drive the resistive divider.
>
> Interesting point about using ADC in burst mode, I do not know if any
> settling time is allowed - the data sheet does not mention it. I just know
> I have seen a lot of inaccuracy if I try to change input then immediately
> start the ADC.
>
> --
> Tim Mitchell
>
>
>
Thanks for the reply. Looks like we're on the same page for the analog
interface.
As for the software side, do you have an example you could share to
illustrate your recommendations to add delays when setting up the ADC?
Thanks,
JS
On Thu, Oct 4, 2012 at 8:42 AM, Tim Mitchell wrote:
> **
> For a higher voltage than 3.3V I would use a resistive divider and a unity
> gain opamp - assuming your source can drive the resistive divider.
>
> Interesting point about using ADC in burst mode, I do not know if any
> settling time is allowed - the data sheet does not mention it. I just know
> I have seen a lot of inaccuracy if I try to change input then immediately
> start the ADC.
>
> --
> Tim Mitchell
>
>
>
Reply by ●October 4, 20122012-10-04
> As for the software side, do you have an example
you
> could share to
> illustrate your recommendations to add delays when
> setting up the ADC?
I normally set the next MUX value in the ADC interrupt, then set a flag which is read in a general purpose timer interrupt, after a few ticks of that I then trigger the next conversion.
--
Tim Mitchell
> could share to
> illustrate your recommendations to add delays when
> setting up the ADC?
I normally set the next MUX value in the ADC interrupt, then set a flag which is read in a general purpose timer interrupt, after a few ticks of that I then trigger the next conversion.
--
Tim Mitchell
