Hi

Where can I check the available interrupt priority levels for a certain
device?

For example LPC13xx and LPC13Uxx use an M3 core but unlike the LPC177x
have just 8 priority levels (using just three bits), where can I find
that info?
It is not in the user manual, the LPC13xx manual points to "See the ARM
Cortex-M3 technical reference manual." but the M3 reference is the same
for all M3 based mcu

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihgjeed.html

Alex
---------------------
http://alexan.edaboard.eu/ (Home of ARMwizard, a free tool for peripheral initialization of LPC2xxx/17xx/13xx/11xx microcontrollers ) Start a New Thread

Actually now I'm getting confused.
In Keil Uvision v4.60 I find the following info:

C:\Keil\ARM\INC\NXP\LPC13xx in file LPC13xx.h (used for LPC1311/13/42/43)
------------------------------
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for
Priority Levels */
C:\Keil\ARM\INC\NXP\LPC13Uxx in file LPC13Uxx.h (used for
LPC1315/16/17/45/46/47)
------------------------------
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for
Priority Levels */
C:\Keil\ARM\INC\NXP\LPC177x_8x in file LPC177x_8x.h
------------------------------
#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for
Priority Levels */
I know that the 5bit priority definition is correct for LPC177x/8x, it
is shown in the register description in the user manual.

The LPC13xx header (LPC1311/13/42/43) that shows 3bit definition seems
to be wrong because in the user manual (UM10375) it says "Each interrupt
can have one of 32 priorities, where 0 is the highest priority." in the
register description.

I have no idea about LPC13Uxx header (LPC1315/16/17/45/46/47), there is
just a hint in UM10525 in the feature headlines "8 programmable
interrupt priority levels with hardware priority level masking" but
there is no register description in the manual because it points to the
Cortex-M3 technical reference manual as I mentioned previously.

So where can I find a description of the LPC13Uxx priority registers
that shows if they use 3 or 5 bits?
Alex
---------------------
http://alexan.edaboard.eu/ (Home of ARMwizard, a free tool for peripheral initialization of LPC2xxx/17xx/13xx/11xx microcontrollers ) Start a New Thread

Hi Alex,

LPC13xx User Manual (UM10375) is most probably wrong wherever it refers to 32 priority levels.

On page 79,section 6.6.11 and following sections, for instance, in describing Interrupt Priority Register 0 (it goes up to 14), it wrongly states that there are 32 priority levels, BUT the bit positions assigned are just 3, like 7:5, or 31:29. Also in the description, it states:

7:5 IP_PIO0_0 PIO0_0 Interrupt Priority. 0 = highest priority. 7 = lowest priority

clearly showing just three bits for the eight levels.

Julio de Melo Start a New Thread

Yes , you are right, I didn't notice that, the description says 0-31
but the bits shown are three.
I just hope that the error lies in the description and not in the
registers shown because either the text is wrong or the registers shown.
I wonder now if it is possible to find any source that shows the
priority bits for LPC1315/16/17/45/46/47 (LPC13Uxx) so that we can
verify that it is three bits too.

Alex
---------------------
http://alexan.edaboard.eu/ (Home of ARMwizard, a free tool for peripheral initialization of LPC2xxx/17xx/13xx/11xx microcontrollers ) Start a New Thread

--- In l..., Alexan_e wrote:
>
> I wonder now if it is possible to find any source that shows the
> priority bits for LPC1315/16/17/45/46/47 (LPC13Uxx) so that we can
> verify that it is three bits too.
>

I can confirm that the source code supplied for use with the LPCXpresso LPC1347 boards uses three bits for the priority values,

Regards,
Chris

--
Chris Burrows
Astrobe for Cortex-M3 (v4.3 Nov 2012)
http://www.astrobe.com Start a New Thread

Yes, check out the core_cm3.c and lpc???_system.c file from NXP. They
(should) get those info correct in the source code. Start a New Thread

> I can confirm that the source code supplied for use with the
> LPCXpresso LPC1347 boards uses three bits for the priority values,

Thank you, it is good to have a cross reference
On 12/08/2012 04:10 AM, Richard Man wrote:

> Yes, check out the core_cm3.c and lpc???_system.c file from NXP. They
> (should) get those info correct in the source code.

The content of these files include the M3 core priority functions but
they are based on the __NVIC_PRIO_BITS define.
The actual bit definition is in the individual family headers and the
values are the ones I mentioned in the previous email.

I guess for now we can assume that the NXP headers are correct.

Thank you all

Alex
---------------------
http://alexan.edaboard.eu/ (Home of ARMwizard, a free tool for peripheral initialization of LPC2xxx/17xx/13xx/11xx/122x microcontrollers ) Start a New Thread

If you have access to the device, can you just try writing 0xFF to one of the priority registers, read it back, and then count the number of 1 bits that are maintained? The ARMv7M docs appears to indicate that the unused bits for a device should be RAZ.

For example this code:



If I run that code on my mbed-LPC1768 based device, I get the following output:
NVIC->IP[0] = 00000000
NVIC->IP[0] = 000000F8

This matches the 5 bits specified in the __NVIC_PRIO_BITS define of the LPC17xx CMSIS headers and the LPC17xx documentation. Start a New Thread

Unfortunately I don't have any LPC13xx chip.
I have received a bug report because my application generates code like
the following for all LPC13xx
NVIC_SetPriority(SSP0_IRQn,0); /* Default priority group 0, can
be 0(highest) - 31(lowest) */
so the suggested range in the comment is wrong for both LPC13xx and
13Uxx families and I would like to be certain of the correct range
before I change it so that I can get it right this time.
Alex
---------------------
http://alexan.edaboard.eu/ (Home of ARMwizard, a free tool for peripheral initialization of LPC2xxx/17xx/13xx/11xx/122x microcontrollers ) Start a New Thread

> Unfortunately I don't have any LPC13xx chip.
> I have received a bug report because my application generates code like
> the following for all LPC13xx
> NVIC_SetPriority(SSP0_IRQn,0); /* Default priority group 0, can
> be 0(highest) - 31(lowest) */
> so the suggested range in the comment is wrong for both LPC13xx and
> 13Uxx families and I would like to be certain of the correct range
> before I change it so that I can get it right this time.

Both the LPC1347 and the LPC1343 priority registers read as 0xE0 when 0xFF is written them which is what you would expect for 3 bits,

Regards,
Chris

--
Chris Burrows
Astrobe for Cortex-M3 (v4.3 Nov 2012)
http://www.astrobe.com

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