Hi,
I am currently fighting to get an EA LPC4357 OEM board to work with 204MHz
core clock, but EMC or SDRAM is only working up to 144MHz.
Anyone got the LPC4357 work with > 144MHz?
Yes, the EMC clock is set to /2 otherwise I can only go up to 96MHz.
Strange, the register CLK_EMCDIV_CFG is written with 0x21 and changes to
0x08000001, which is not a documented value.
Any hint?
--
42Bastian
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
LPC4357 && 204MHz && SDRAM ??
Started by ●February 3, 2013
Reply by ●February 4, 20132013-02-04
Ha!
We(my colleague and me from time to time) have spent 2 weeks for searching for reasons of troubles with DRAM on our own PCB with LPC43 and "I'm going slightly mad" : problem started as "sprintf does not add final zero under FreeRTOS" is still actual :(
What memory type is used in EA board?
Best regards
Vlad
----- Original Message -----
From: 42Bastian
To: l...
Sent: Sunday, February 03, 2013 11:49 PM
Subject: [lpc2000] LPC4357 && 204MHz && SDRAM ??
Hi,
I am currently fighting to get an EA LPC4357 OEM board to work with 204MHz
core clock, but EMC or SDRAM is only working up to 144MHz.
Anyone got the LPC4357 work with > 144MHz?
Yes, the EMC clock is set to /2 otherwise I can only go up to 96MHz.
Strange, the register CLK_EMCDIV_CFG is written with 0x21 and changes to
0x08000001, which is not a documented value.
Any hint?
--
42Bastian
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
We(my colleague and me from time to time) have spent 2 weeks for searching for reasons of troubles with DRAM on our own PCB with LPC43 and "I'm going slightly mad" : problem started as "sprintf does not add final zero under FreeRTOS" is still actual :(
What memory type is used in EA board?
Best regards
Vlad
----- Original Message -----
From: 42Bastian
To: l...
Sent: Sunday, February 03, 2013 11:49 PM
Subject: [lpc2000] LPC4357 && 204MHz && SDRAM ??
Hi,
I am currently fighting to get an EA LPC4357 OEM board to work with 204MHz
core clock, but EMC or SDRAM is only working up to 144MHz.
Anyone got the LPC4357 work with > 144MHz?
Yes, the EMC clock is set to /2 otherwise I can only go up to 96MHz.
Strange, the register CLK_EMCDIV_CFG is written with 0x21 and changes to
0x08000001, which is not a documented value.
Any hint?
--
42Bastian
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
Reply by ●February 4, 20132013-02-04
Hi Vladimir
>
> We(my colleague and me from time to time) have spent 2 weeks for
> searching for reasons of troubles with DRAM on our own PCB with LPC43
> and "I'm going slightly mad" : problem started as "sprintf does not add
> final zero under FreeRTOS" is still actual :( What memory type is used
> in EA board?
It is a ISSI SDRAM (256Mbit). I do not think the SDRAM is the problem as
it is specified for 100MHz bus with CAS-latency of 2.
The strange is, any example I find seems to be a modified copy of NXP code
which states:
//Timing for 48/60/72MHZ Bus
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
>
> We(my colleague and me from time to time) have spent 2 weeks for
> searching for reasons of troubles with DRAM on our own PCB with LPC43
> and "I'm going slightly mad" : problem started as "sprintf does not add
> final zero under FreeRTOS" is still actual :( What memory type is used
> in EA board?
It is a ISSI SDRAM (256Mbit). I do not think the SDRAM is the problem as
it is specified for 100MHz bus with CAS-latency of 2.
The strange is, any example I find seems to be a modified copy of NXP code
which states:
//Timing for 48/60/72MHZ Bus
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
Reply by ●February 4, 20132013-02-04
Hi Bastian,
>>It is a ISSI SDRAM (256Mbit). I do not think the SDRAM is the problem as
it is specified for 100MHz bus with CAS-latency of 2.
We have evaluation kit from Keil working well, there is 32bit SDRAM on it.
Porting project to our PCB (where we use 256 Mbit 16 bit SDRAM - similar to yourth, but from Micron) fails.
Are you sure that your SDRAM really works on any frequency? I doubt because:
1) We have situation that simple test passes without problems but more complicate test does not pass.
2) Attempt to reduce bus frequency in two times to 60 MHz was unsuccessful.
WBR
Vladimir
----- Original Message -----
From: 42Bastian
To: l...
Sent: Monday, February 04, 2013 9:22 AM
Subject: Re: [lpc2000] LPC4357 && 204MHz && SDRAM ??
Hi Vladimir
>
> We(my colleague and me from time to time) have spent 2 weeks for
> searching for reasons of troubles with DRAM on our own PCB with LPC43
> and "I'm going slightly mad" : problem started as "sprintf does not add
> final zero under FreeRTOS" is still actual :( What memory type is used
> in EA board?
It is a ISSI SDRAM (256Mbit). I do not think the SDRAM is the problem as
it is specified for 100MHz bus with CAS-latency of 2.
The strange is, any example I find seems to be a modified copy of NXP code
which states:
//Timing for 48/60/72MHZ Bus
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
>>It is a ISSI SDRAM (256Mbit). I do not think the SDRAM is the problem as
it is specified for 100MHz bus with CAS-latency of 2.
We have evaluation kit from Keil working well, there is 32bit SDRAM on it.
Porting project to our PCB (where we use 256 Mbit 16 bit SDRAM - similar to yourth, but from Micron) fails.
Are you sure that your SDRAM really works on any frequency? I doubt because:
1) We have situation that simple test passes without problems but more complicate test does not pass.
2) Attempt to reduce bus frequency in two times to 60 MHz was unsuccessful.
WBR
Vladimir
----- Original Message -----
From: 42Bastian
To: l...
Sent: Monday, February 04, 2013 9:22 AM
Subject: Re: [lpc2000] LPC4357 && 204MHz && SDRAM ??
Hi Vladimir
>
> We(my colleague and me from time to time) have spent 2 weeks for
> searching for reasons of troubles with DRAM on our own PCB with LPC43
> and "I'm going slightly mad" : problem started as "sprintf does not add
> final zero under FreeRTOS" is still actual :( What memory type is used
> in EA board?
It is a ISSI SDRAM (256Mbit). I do not think the SDRAM is the problem as
it is specified for 100MHz bus with CAS-latency of 2.
The strange is, any example I find seems to be a modified copy of NXP code
which states:
//Timing for 48/60/72MHZ Bus
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
Reply by ●February 4, 20132013-02-04
Hi Vladimir
>>> It is a ISSI SDRAM (256Mbit). I do not think the SDRAM is the
>>> problem as
> it is specified for 100MHz bus with CAS-latency of 2.
>
> We have evaluation kit from Keil working well, there is 32bit SDRAM on
> it.
Which speed?
> Porting project to our PCB (where we use 256 Mbit 16 bit SDRAM -
> similar to yourth, but from Micron) fails. Are you sure that your SDRAM
> really works on any frequency?
No, not sure at all. The simple EA SDRAM test passes, but I see strange
values if I fill the SDRAM via Debugger. But then, can I trust the debugger.
I fear I have to write some more sophisticated test.
> I doubt because: 1) We have situation
> that simple test passes without problems but more complicate test does
> not pass. 2) Attempt to reduce bus frequency in two times to 60 MHz was
> unsuccessful.
To be honest, I rely on the EA code (which is a copy of NXP code). I am
not that fit when it comes to SDRAMs and all the timing stuff.
But what makes me wonder is, if I run the CPU with 96MHz, I can use 1:1
clock for EMC and the CPU and SDRAM works (at least no crash).
If I choose 1:2 ration, I can only go up to 144MHz?
Cheers
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
>>> It is a ISSI SDRAM (256Mbit). I do not think the SDRAM is the
>>> problem as
> it is specified for 100MHz bus with CAS-latency of 2.
>
> We have evaluation kit from Keil working well, there is 32bit SDRAM on
> it.
Which speed?
> Porting project to our PCB (where we use 256 Mbit 16 bit SDRAM -
> similar to yourth, but from Micron) fails. Are you sure that your SDRAM
> really works on any frequency?
No, not sure at all. The simple EA SDRAM test passes, but I see strange
values if I fill the SDRAM via Debugger. But then, can I trust the debugger.
I fear I have to write some more sophisticated test.
> I doubt because: 1) We have situation
> that simple test passes without problems but more complicate test does
> not pass. 2) Attempt to reduce bus frequency in two times to 60 MHz was
> unsuccessful.
To be honest, I rely on the EA code (which is a copy of NXP code). I am
not that fit when it comes to SDRAMs and all the timing stuff.
But what makes me wonder is, if I run the CPU with 96MHz, I can use 1:1
clock for EMC and the CPU and SDRAM works (at least no crash).
If I choose 1:2 ration, I can only go up to 144MHz?
Cheers
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
Reply by ●February 4, 20132013-02-04
Hi Bastian,
>> Which speed?
120 MHz and code from NXP, implemented by ourself (there was not any project from Keil).
So, NXP code must work, at least in some conditions.
>>No, not sure at all. The simple EA SDRAM test passes, but I see strange
values if I fill the SDRAM via Debugger. But then, can I trust the debugger.
Yes, topic of trust the debugger is way to nowhere :)
We did following test:
- simple block write/block read test runs in main() and checks area A of SDRAM
- few hundreds write/read operations into area B of SDRAM implemented into system tick ISR
Result: test fails
If to remove all operations with SDRAM in ISR, then result=OK
I kindly ask you to run similar test to be sure are our problems similar or we have two different situations. Thanks.
>>If I choose 1:2 ration, I can only go up to 144MHz?
Why 144?
With 1:2 ratio you can use 204 CPU clock and 104 SDRAM clock.
WBR
Vladimir
----- Original Message -----
From: 42Bastian
To: l...
Sent: Monday, February 04, 2013 10:43 AM
Subject: Re: [lpc2000] LPC4357 && 204MHz && SDRAM ??
Hi Vladimir
>>> It is a ISSI SDRAM (256Mbit). I do not think the SDRAM is the
>>> problem as
> it is specified for 100MHz bus with CAS-latency of 2.
>
> We have evaluation kit from Keil working well, there is 32bit SDRAM on
> it.
Which speed?
> Porting project to our PCB (where we use 256 Mbit 16 bit SDRAM -
> similar to yourth, but from Micron) fails. Are you sure that your SDRAM
> really works on any frequency?
No, not sure at all. The simple EA SDRAM test passes, but I see strange
values if I fill the SDRAM via Debugger. But then, can I trust the debugger.
I fear I have to write some more sophisticated test.
> I doubt because: 1) We have situation
> that simple test passes without problems but more complicate test does
> not pass. 2) Attempt to reduce bus frequency in two times to 60 MHz was
> unsuccessful.
To be honest, I rely on the EA code (which is a copy of NXP code). I am
not that fit when it comes to SDRAMs and all the timing stuff.
But what makes me wonder is, if I run the CPU with 96MHz, I can use 1:1
clock for EMC and the CPU and SDRAM works (at least no crash).
If I choose 1:2 ration, I can only go up to 144MHz?
Cheers
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
>> Which speed?
120 MHz and code from NXP, implemented by ourself (there was not any project from Keil).
So, NXP code must work, at least in some conditions.
>>No, not sure at all. The simple EA SDRAM test passes, but I see strange
values if I fill the SDRAM via Debugger. But then, can I trust the debugger.
Yes, topic of trust the debugger is way to nowhere :)
We did following test:
- simple block write/block read test runs in main() and checks area A of SDRAM
- few hundreds write/read operations into area B of SDRAM implemented into system tick ISR
Result: test fails
If to remove all operations with SDRAM in ISR, then result=OK
I kindly ask you to run similar test to be sure are our problems similar or we have two different situations. Thanks.
>>If I choose 1:2 ration, I can only go up to 144MHz?
Why 144?
With 1:2 ratio you can use 204 CPU clock and 104 SDRAM clock.
WBR
Vladimir
----- Original Message -----
From: 42Bastian
To: l...
Sent: Monday, February 04, 2013 10:43 AM
Subject: Re: [lpc2000] LPC4357 && 204MHz && SDRAM ??
Hi Vladimir
>>> It is a ISSI SDRAM (256Mbit). I do not think the SDRAM is the
>>> problem as
> it is specified for 100MHz bus with CAS-latency of 2.
>
> We have evaluation kit from Keil working well, there is 32bit SDRAM on
> it.
Which speed?
> Porting project to our PCB (where we use 256 Mbit 16 bit SDRAM -
> similar to yourth, but from Micron) fails. Are you sure that your SDRAM
> really works on any frequency?
No, not sure at all. The simple EA SDRAM test passes, but I see strange
values if I fill the SDRAM via Debugger. But then, can I trust the debugger.
I fear I have to write some more sophisticated test.
> I doubt because: 1) We have situation
> that simple test passes without problems but more complicate test does
> not pass. 2) Attempt to reduce bus frequency in two times to 60 MHz was
> unsuccessful.
To be honest, I rely on the EA code (which is a copy of NXP code). I am
not that fit when it comes to SDRAMs and all the timing stuff.
But what makes me wonder is, if I run the CPU with 96MHz, I can use 1:1
clock for EMC and the CPU and SDRAM works (at least no crash).
If I choose 1:2 ration, I can only go up to 144MHz?
Cheers
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
Reply by ●February 4, 20132013-02-04
Hi Vladimir
>>> Which speed?
> 120 MHz and code from NXP, implemented by ourself (there was not any project from Keil).
> So, NXP code must work, at least in some conditions.
120MHz Core clock and 60MHz EMC?
>>> No, not sure at all. The simple EA SDRAM test passes, but I see strange
> values if I fill the SDRAM via Debugger. But then, can I trust the debugger.
> Yes, topic of trust the debugger is way to nowhere :)
> We did following test:
> - simple block write/block read test runs in main() and checks area A of SDRAM
> - few hundreds write/read operations into area B of SDRAM implemented into system tick ISR
> Result: test fails
> If to remove all operations with SDRAM in ISR, then result=OK
> I kindly ask you to run similar test to be sure are our problems similar or we have two different situations. Thanks.
I will try it tomorrow.
>>> If I choose 1:2 ration, I can only go up to 144MHz?
> Why 144?
> With 1:2 ratio you can use 204 CPU clock and 104 SDRAM clock.
Yes. That's where I am not sure I am hunting false bugs.
If I uses 96MHz core clock and 1:1 ratio for EMC, the SDRAM "seems" to
work (at least the memory can be seen).
If I uses 1:2 ration, I cannot go higher with the core clock than 144MHz
(giving 72MHz to the EMC).
Cheers
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
>>> Which speed?
> 120 MHz and code from NXP, implemented by ourself (there was not any project from Keil).
> So, NXP code must work, at least in some conditions.
120MHz Core clock and 60MHz EMC?
>>> No, not sure at all. The simple EA SDRAM test passes, but I see strange
> values if I fill the SDRAM via Debugger. But then, can I trust the debugger.
> Yes, topic of trust the debugger is way to nowhere :)
> We did following test:
> - simple block write/block read test runs in main() and checks area A of SDRAM
> - few hundreds write/read operations into area B of SDRAM implemented into system tick ISR
> Result: test fails
> If to remove all operations with SDRAM in ISR, then result=OK
> I kindly ask you to run similar test to be sure are our problems similar or we have two different situations. Thanks.
I will try it tomorrow.
>>> If I choose 1:2 ration, I can only go up to 144MHz?
> Why 144?
> With 1:2 ratio you can use 204 CPU clock and 104 SDRAM clock.
Yes. That's where I am not sure I am hunting false bugs.
If I uses 96MHz core clock and 1:1 ratio for EMC, the SDRAM "seems" to
work (at least the memory can be seen).
If I uses 1:2 ration, I cannot go higher with the core clock than 144MHz
(giving 72MHz to the EMC).
Cheers
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
Reply by ●February 4, 20132013-02-04
Hi Bastian,
>> 120MHz Core clock and 60MHz EMC?
No, 1:1 : 120 CPU and 120 EMC.
>> I will try it tomorrow.
It would be nice.
If you are interested in my init code - no problem, I can send it. My interest is EA schematic.
WBR
Vladimir
----- Original Message -----
From: 42Bastian
To: l...
Sent: Monday, February 04, 2013 12:17 PM
Subject: Re: [lpc2000] LPC4357 && 204MHz && SDRAM ??
Hi Vladimir
>>> Which speed?
> 120 MHz and code from NXP, implemented by ourself (there was not any project from Keil).
> So, NXP code must work, at least in some conditions.
120MHz Core clock and 60MHz EMC?
>>> No, not sure at all. The simple EA SDRAM test passes, but I see strange
> values if I fill the SDRAM via Debugger. But then, can I trust the debugger.
> Yes, topic of trust the debugger is way to nowhere :)
> We did following test:
> - simple block write/block read test runs in main() and checks area A of SDRAM
> - few hundreds write/read operations into area B of SDRAM implemented into system tick ISR
> Result: test fails
> If to remove all operations with SDRAM in ISR, then result=OK
> I kindly ask you to run similar test to be sure are our problems similar or we have two different situations. Thanks.
I will try it tomorrow.
>>> If I choose 1:2 ration, I can only go up to 144MHz?
> Why 144?
> With 1:2 ratio you can use 204 CPU clock and 104 SDRAM clock.
Yes. That's where I am not sure I am hunting false bugs.
If I uses 96MHz core clock and 1:1 ratio for EMC, the SDRAM "seems" to
work (at least the memory can be seen).
If I uses 1:2 ration, I cannot go higher with the core clock than 144MHz
(giving 72MHz to the EMC).
Cheers
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
>> 120MHz Core clock and 60MHz EMC?
No, 1:1 : 120 CPU and 120 EMC.
>> I will try it tomorrow.
It would be nice.
If you are interested in my init code - no problem, I can send it. My interest is EA schematic.
WBR
Vladimir
----- Original Message -----
From: 42Bastian
To: l...
Sent: Monday, February 04, 2013 12:17 PM
Subject: Re: [lpc2000] LPC4357 && 204MHz && SDRAM ??
Hi Vladimir
>>> Which speed?
> 120 MHz and code from NXP, implemented by ourself (there was not any project from Keil).
> So, NXP code must work, at least in some conditions.
120MHz Core clock and 60MHz EMC?
>>> No, not sure at all. The simple EA SDRAM test passes, but I see strange
> values if I fill the SDRAM via Debugger. But then, can I trust the debugger.
> Yes, topic of trust the debugger is way to nowhere :)
> We did following test:
> - simple block write/block read test runs in main() and checks area A of SDRAM
> - few hundreds write/read operations into area B of SDRAM implemented into system tick ISR
> Result: test fails
> If to remove all operations with SDRAM in ISR, then result=OK
> I kindly ask you to run similar test to be sure are our problems similar or we have two different situations. Thanks.
I will try it tomorrow.
>>> If I choose 1:2 ration, I can only go up to 144MHz?
> Why 144?
> With 1:2 ratio you can use 204 CPU clock and 104 SDRAM clock.
Yes. That's where I am not sure I am hunting false bugs.
If I uses 96MHz core clock and 1:1 ratio for EMC, the SDRAM "seems" to
work (at least the memory can be seen).
If I uses 1:2 ration, I cannot go higher with the core clock than 144MHz
(giving 72MHz to the EMC).
Cheers
--
42Bastian
+
| http://www.sciopta.com
| Fastest direct message passing kernel.
| IEC61508 certified.
+
Reply by ●February 4, 20132013-02-04
Il 04/02/2013 10:17, 42Bastian ha scritto:
>
>
> Hi Vladimir
>
> >>> Which speed?
> > 120 MHz and code from NXP, implemented by ourself (there was not any
> project from Keil).
> > So, NXP code must work, at least in some conditions.
>
> 120MHz Core clock and 60MHz EMC?
>
> >>> No, not sure at all. The simple EA SDRAM test passes, but I see
> strange
> > values if I fill the SDRAM via Debugger. But then, can I trust the
> debugger.
> > Yes, topic of trust the debugger is way to nowhere :)
> > We did following test:
> > - simple block write/block read test runs in main() and checks area
> A of SDRAM
> > - few hundreds write/read operations into area B of SDRAM
> implemented into system tick ISR
> > Result: test fails
> > If to remove all operations with SDRAM in ISR, then result=OK
>
If there is no sw error this should be a problem related to refresh DRAM
frequency you should rise the refresh frequency and see if solves the
problem. I had no problems related to DRAM when I debugged LPC4357 with
the Hitex beta board.
>
> > I kindly ask you to run similar test to be sure are our problems
> similar or we have two different situations. Thanks.
>
> I will try it tomorrow.
>
> >>> If I choose 1:2 ration, I can only go up to 144MHz?
> > Why 144?
> > With 1:2 ratio you can use 204 CPU clock and 104 SDRAM clock.
>
> Yes. That's where I am not sure I am hunting false bugs.
>
> If I uses 96MHz core clock and 1:1 ratio for EMC, the SDRAM "seems" to
> work (at least the memory can be seen).
> If I uses 1:2 ration, I cannot go higher with the core clock than 144MHz
> (giving 72MHz to the EMC).
>
> Cheers
>
> --
> 42Bastian
> +
> | http://www.sciopta.com
> | Fastest direct message passing kernel.
> | IEC61508 certified.
> +
>
>
> Hi Vladimir
>
> >>> Which speed?
> > 120 MHz and code from NXP, implemented by ourself (there was not any
> project from Keil).
> > So, NXP code must work, at least in some conditions.
>
> 120MHz Core clock and 60MHz EMC?
>
> >>> No, not sure at all. The simple EA SDRAM test passes, but I see
> strange
> > values if I fill the SDRAM via Debugger. But then, can I trust the
> debugger.
> > Yes, topic of trust the debugger is way to nowhere :)
> > We did following test:
> > - simple block write/block read test runs in main() and checks area
> A of SDRAM
> > - few hundreds write/read operations into area B of SDRAM
> implemented into system tick ISR
> > Result: test fails
> > If to remove all operations with SDRAM in ISR, then result=OK
>
If there is no sw error this should be a problem related to refresh DRAM
frequency you should rise the refresh frequency and see if solves the
problem. I had no problems related to DRAM when I debugged LPC4357 with
the Hitex beta board.
>
> > I kindly ask you to run similar test to be sure are our problems
> similar or we have two different situations. Thanks.
>
> I will try it tomorrow.
>
> >>> If I choose 1:2 ration, I can only go up to 144MHz?
> > Why 144?
> > With 1:2 ratio you can use 204 CPU clock and 104 SDRAM clock.
>
> Yes. That's where I am not sure I am hunting false bugs.
>
> If I uses 96MHz core clock and 1:1 ratio for EMC, the SDRAM "seems" to
> work (at least the memory can be seen).
> If I uses 1:2 ration, I cannot go higher with the core clock than 144MHz
> (giving 72MHz to the EMC).
>
> Cheers
>
> --
> 42Bastian
> +
> | http://www.sciopta.com
> | Fastest direct message passing kernel.
> | IEC61508 certified.
> +
Reply by ●February 5, 20132013-02-05
Hi,
>>you should rise the refresh frequency and see if solves the
>>problem.
We did it without success.
And how refresh could be a reason that data written in one cell influences on the other cell?
>>>I had no problems related to DRAM when I debugged LPC4357 with
the Hitex
My congratulation!
I don't exclude stupid mistake in init code, but I lost hope to find it.
Best regards
Vladimir
----- Original Message -----
From: M. Manca
To: l...
Sent: Monday, February 04, 2013 1:45 PM
Subject: Re: [lpc2000] LPC4357 && 204MHz && SDRAM ??
Il 04/02/2013 10:17, 42Bastian ha scritto:
>
>
> Hi Vladimir
>
> >>> Which speed?
> > 120 MHz and code from NXP, implemented by ourself (there was not any
> project from Keil).
> > So, NXP code must work, at least in some conditions.
>
> 120MHz Core clock and 60MHz EMC?
>
> >>> No, not sure at all. The simple EA SDRAM test passes, but I see
> strange
> > values if I fill the SDRAM via Debugger. But then, can I trust the
> debugger.
> > Yes, topic of trust the debugger is way to nowhere :)
> > We did following test:
> > - simple block write/block read test runs in main() and checks area
> A of SDRAM
> > - few hundreds write/read operations into area B of SDRAM
> implemented into system tick ISR
> > Result: test fails
> > If to remove all operations with SDRAM in ISR, then result=OK
>
If there is no sw error this should be a problem related to refresh DRAM
frequency you should rise the refresh frequency and see if solves the
problem. I had no problems related to DRAM when I debugged LPC4357 with
the Hitex beta board.
>
> > I kindly ask you to run similar test to be sure are our problems
> similar or we have two different situations. Thanks.
>
> I will try it tomorrow.
>
> >>> If I choose 1:2 ration, I can only go up to 144MHz?
> > Why 144?
> > With 1:2 ratio you can use 204 CPU clock and 104 SDRAM clock.
>
> Yes. That's where I am not sure I am hunting false bugs.
>
> If I uses 96MHz core clock and 1:1 ratio for EMC, the SDRAM "seems" to
> work (at least the memory can be seen).
> If I uses 1:2 ration, I cannot go higher with the core clock than 144MHz
> (giving 72MHz to the EMC).
>
> Cheers
>
> --
> 42Bastian
> +
> | http://www.sciopta.com
> | Fastest direct message passing kernel.
> | IEC61508 certified.
> +
>
>
>>you should rise the refresh frequency and see if solves the
>>problem.
We did it without success.
And how refresh could be a reason that data written in one cell influences on the other cell?
>>>I had no problems related to DRAM when I debugged LPC4357 with
the Hitex
My congratulation!
I don't exclude stupid mistake in init code, but I lost hope to find it.
Best regards
Vladimir
----- Original Message -----
From: M. Manca
To: l...
Sent: Monday, February 04, 2013 1:45 PM
Subject: Re: [lpc2000] LPC4357 && 204MHz && SDRAM ??
Il 04/02/2013 10:17, 42Bastian ha scritto:
>
>
> Hi Vladimir
>
> >>> Which speed?
> > 120 MHz and code from NXP, implemented by ourself (there was not any
> project from Keil).
> > So, NXP code must work, at least in some conditions.
>
> 120MHz Core clock and 60MHz EMC?
>
> >>> No, not sure at all. The simple EA SDRAM test passes, but I see
> strange
> > values if I fill the SDRAM via Debugger. But then, can I trust the
> debugger.
> > Yes, topic of trust the debugger is way to nowhere :)
> > We did following test:
> > - simple block write/block read test runs in main() and checks area
> A of SDRAM
> > - few hundreds write/read operations into area B of SDRAM
> implemented into system tick ISR
> > Result: test fails
> > If to remove all operations with SDRAM in ISR, then result=OK
>
If there is no sw error this should be a problem related to refresh DRAM
frequency you should rise the refresh frequency and see if solves the
problem. I had no problems related to DRAM when I debugged LPC4357 with
the Hitex beta board.
>
> > I kindly ask you to run similar test to be sure are our problems
> similar or we have two different situations. Thanks.
>
> I will try it tomorrow.
>
> >>> If I choose 1:2 ration, I can only go up to 144MHz?
> > Why 144?
> > With 1:2 ratio you can use 204 CPU clock and 104 SDRAM clock.
>
> Yes. That's where I am not sure I am hunting false bugs.
>
> If I uses 96MHz core clock and 1:1 ratio for EMC, the SDRAM "seems" to
> work (at least the memory can be seen).
> If I uses 1:2 ration, I cannot go higher with the core clock than 144MHz
> (giving 72MHz to the EMC).
>
> Cheers
>
> --
> 42Bastian
> +
> | http://www.sciopta.com
> | Fastest direct message passing kernel.
> | IEC61508 certified.
> +
>
>
