Hello,

i have a question about the configuration of SPI/SSI,
not directly related to a certain chip of NXP,
but currently using a LPC812.

I have connected a AS5045 (hall sensor IC),
which offers a Synchronous Serial Interface:
(see figure 5 on bottom of page 13)

http://www.ams.com/content/download/1288/7223/AS5045_Datasheet_v1_7.pdf

It uses only a CS and CLK, and sends data to uC.
Data from uC to sensor IC is not needed, sending only dummy data,
to get SPI running.

I control CS on my own. CPOL=1, CPHA=0, FrameLength (or 12)
data is sampled/captured on CLK going from HIGH to LOW.

Problem is, that first bit (D11) is not going as highest bit
into receive data, but it is one bit shifted.
I think this comes from an additional clock cycle
at the beginning, when AS5045 is sending data.

E.g. compare to picture from wikipedia

http://en.wikipedia.org/wiki/File:SPI_timing_diagram2.svg

Is there some bit to control such behavior in hardware,
or is the only way to discard the bit and shift the value
manually by software?

I am currently using a FrameLength of 13 bits,
so i get the bit i discard plus the 12 bit of the sensor,
and second 13 bits, which contains status and dummy bits.
(2 times 10 bits would also be possible, minimum 19 bits)

Best regards,

Martin

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On 18.02.2013 20:12, capiman26061973 wrote:
> ...
> I control CS on my own. CPOL=1, CPHA=0, FrameLength (or 12)
> data is sampled/captured on CLK going from HIGH to LOW.
>
> Problem is, that first bit (D11) is not going as highest bit
> into receive data, but it is one bit shifted.
> ...
> Is there some bit to control such behavior in hardware,
> or is the only way to discard the bit and shift the value
> manually by software?

Comparing the datasheet of the sensor to the UM of LPC2101 (don't have
LPC812 UM handy), I would try CPOL=0, CPHA=1...

--

Timo

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