Hi,
I am looking at counting the execution time of a piece of code and am
unclear about the timings involved when the constant generator registers (R2
and R3) are used. I'm using the CPUX core in the 2619 variant, but the
small
data model so most of the instructions are not extended.
My particular confusion is about the following line (from IAR's
listing):
D2B30300 BIT.B #0x1, &0x3
Pretty straightforward. #0x1 will be taken as 0(R3), destination is absolute
address. Looking in the Format I instruction cycles and lengths I can see
that the x(Rx),&TONI gives 6 cycles. I can reduce by 1 because it's a
BIT
instruction.
I think I can reduce it again by 1 because the value for x is implicit in
the instruction and not stored in memory. Is that correct? Disassembling
using naken430 gives a cycle count of 4, and that's the only reason I
can
think that it is 2 cycles lower than what the user guide says for those
addressing modes.
Thanks.
Cycle counts for constant generator registers
Started by ●September 14, 2012
Reply by ●September 14, 20122012-09-14
Hello,
I'm currently in a class that is currently studying the MSP430 CPU. It is not the CPUX, but they use the same User's Guide (SLAU144). That said, I think I see what is going on. Looking at the Table for Format I Instruction Cycles and Lengths (SLAU144i, pg 150), it appears that you are looking at the source block. From my understanding, #0x1 is treated as an Rn source, not an x(Rn) source. This would bring the cycle count to 4 before the application of the footnote. After the footnote, the total number of cycles would be 3 (I am not 100% sure that I am applying it correctly though). Could it be that naken430 does not take the footnote into account?
How to get this answer by constructing the instruction by hand:
Figure 4-21 (pg 144) shows the format of Double-Operand instructions.
Starting with the first word of the instruction. According to Table 4-20 (pg 164), BIT.B has an OPCODE of Bxxx. Next, we have the constant value #0x1, which according to Table 4-2 (pg 126), is generated by R3. R3 means that the Rsrc value is 3. The table also states that the AS code is 01. Since this a Bytewise operation, I deduced that the B/W bit would be 1. The destination is &0x3. According to Table 4-3 (pg 127), an absolute address is represented by 01 in the As bits. Now, the system must be able to differentiate between the 3 possible addressing modes, since X(Rn), ADDR, and &ADDR have the same As value. I deduced that the Rdst would have a value of 2 to signify a &ADDR. Table 4-3 and Figure 4-21 show that the destination for an &ADDR is stored (in this case) in the second word. This would be a value of 3. So far, the instruction looks like B3D2 for the first word. Judging by your disassembled code, it is stored "Little Endian". This makes the full instruction D2B30300.
All this was done by RTM.
Timothy Laufer
Senior, Computer Science
________________________________
From: m... [m...] on behalf of David McMinn [d...@intelligentwellcontrols.com]
Sent: Friday, September 14, 2012 3:51 AM
To: MSP430
Subject: [msp430] Cycle counts for constant generator registers
Hi,
I am looking at counting the execution time of a piece of code and am
unclear about the timings involved when the constant generator registers (R2
and R3) are used. I'm using the CPUX core in the 2619 variant, but the small
data model so most of the instructions are not extended.
My particular confusion is about the following line (from IAR's listing):
D2B30300 BIT.B #0x1, &0x3
Pretty straightforward. #0x1 will be taken as 0(R3), destination is absolute
address. Looking in the Format I instruction cycles and lengths I can see
that the x(Rx),&TONI gives 6 cycles. I can reduce by 1 because it's a BIT
instruction.
I think I can reduce it again by 1 because the value for x is implicit in
the instruction and not stored in memory. Is that correct? Disassembling
using naken430 gives a cycle count of 4, and that's the only reason I can
think that it is 2 cycles lower than what the user guide says for those
addressing modes.
Thanks.
I'm currently in a class that is currently studying the MSP430 CPU. It is not the CPUX, but they use the same User's Guide (SLAU144). That said, I think I see what is going on. Looking at the Table for Format I Instruction Cycles and Lengths (SLAU144i, pg 150), it appears that you are looking at the source block. From my understanding, #0x1 is treated as an Rn source, not an x(Rn) source. This would bring the cycle count to 4 before the application of the footnote. After the footnote, the total number of cycles would be 3 (I am not 100% sure that I am applying it correctly though). Could it be that naken430 does not take the footnote into account?
How to get this answer by constructing the instruction by hand:
Figure 4-21 (pg 144) shows the format of Double-Operand instructions.
Starting with the first word of the instruction. According to Table 4-20 (pg 164), BIT.B has an OPCODE of Bxxx. Next, we have the constant value #0x1, which according to Table 4-2 (pg 126), is generated by R3. R3 means that the Rsrc value is 3. The table also states that the AS code is 01. Since this a Bytewise operation, I deduced that the B/W bit would be 1. The destination is &0x3. According to Table 4-3 (pg 127), an absolute address is represented by 01 in the As bits. Now, the system must be able to differentiate between the 3 possible addressing modes, since X(Rn), ADDR, and &ADDR have the same As value. I deduced that the Rdst would have a value of 2 to signify a &ADDR. Table 4-3 and Figure 4-21 show that the destination for an &ADDR is stored (in this case) in the second word. This would be a value of 3. So far, the instruction looks like B3D2 for the first word. Judging by your disassembled code, it is stored "Little Endian". This makes the full instruction D2B30300.
All this was done by RTM.
Timothy Laufer
Senior, Computer Science
________________________________
From: m... [m...] on behalf of David McMinn [d...@intelligentwellcontrols.com]
Sent: Friday, September 14, 2012 3:51 AM
To: MSP430
Subject: [msp430] Cycle counts for constant generator registers
Hi,
I am looking at counting the execution time of a piece of code and am
unclear about the timings involved when the constant generator registers (R2
and R3) are used. I'm using the CPUX core in the 2619 variant, but the small
data model so most of the instructions are not extended.
My particular confusion is about the following line (from IAR's listing):
D2B30300 BIT.B #0x1, &0x3
Pretty straightforward. #0x1 will be taken as 0(R3), destination is absolute
address. Looking in the Format I instruction cycles and lengths I can see
that the x(Rx),&TONI gives 6 cycles. I can reduce by 1 because it's a BIT
instruction.
I think I can reduce it again by 1 because the value for x is implicit in
the instruction and not stored in memory. Is that correct? Disassembling
using naken430 gives a cycle count of 4, and that's the only reason I can
think that it is 2 cycles lower than what the user guide says for those
addressing modes.
Thanks.
Reply by ●September 14, 20122012-09-14
Hi Timothy,
> I'm currently in a class that is currently studying the MSP430 CPU.
> It is not the CPUX, but they use the same User's Guide (SLAU144).
> That said, I think I see what is going on. Looking at the Table for
> Format I Instruction Cycles and Lengths (SLAU144i, pg 150), it
> appears that you are looking at the source block. From my
> understanding, #0x1 is treated as an Rn source, not an x(Rn) source.
Is that stated or implied anywhere in the user manual because that's
what I couldn't find. Looking at sections 4.3.4 on Pg 124 it states that
+1 is R3 with an As value of 01. The example in section 4.3.4.1 on Pg
124 shows how the assembler would convert #1 to 0(R3).
Coupled with that, you can use the SR as a source or destination in Rn
mode, so it appeared to me that the modes were distinct.
The closest implication I found was in section 3.2.4 where it says
"Registers R2 and R3, used in the constant mode, cannot be addressed
explicitly; they act as source-only registers" but it's hardly a
definitive statement that the source addressing mode used is Rx.
> This would bring the cycle count to 4 before the application of the
> footnote. After the footnote, the total number of cycles would be 3
> (I am not 100% sure that I am applying it correctly though). Could it
> be that naken430 does not take the footnote into account?
I think my use of naken430 has thrown me (and this question) off
somewhat. It only supports the CPU core, not the CPUX core. When I look
at the instruction execution timings for the CPU "Rx,&EDE" is 4 cycles
without any footnotes.
So your statement that #0x1 is treated as an Rn source fits that too.
> How to get this answer by constructing the instruction by hand:
[...]
> All this was done by RTM.
Indeed, that's all written in the manual. And that's where I looked
first. But I haven't seen a definitive statement that says the constant
generators behave as register mode source for the purposes of execution
times. Perhaps it's just assumed that it's the only way they could work.
> Timothy Laufer Senior, Computer Science
> ________________________________ From: m...
> [m...] on behalf of David McMinn
> [d...@intelligentwellcontrols.com] Sent: Friday, September
> 14, 2012 3:51 AM To: MSP430 Subject: [msp430] Cycle counts for
> constant generator registers
>
> Hi,
>
> I am looking at counting the execution time of a piece of code and
> am unclear about the timings involved when the constant generator
> registers (R2 and R3) are used. I'm using the CPUX core in the 2619
> variant, but the small data model so most of the instructions are not
> extended.
>
> My particular confusion is about the following line (from IAR's
> listing):
>
> D2B30300 BIT.B #0x1, &0x3
>
> Pretty straightforward. #0x1 will be taken as 0(R3), destination is
> absolute address. Looking in the Format I instruction cycles and
> lengths I can see that the x(Rx),&TONI gives 6 cycles. I can reduce
> by 1 because it's a BIT instruction.
>
> I think I can reduce it again by 1 because the value for x is
> implicit in the instruction and not stored in memory. Is that
> correct? Disassembling using naken430 gives a cycle count of 4, and
> that's the only reason I can think that it is 2 cycles lower than
> what the user guide says for those addressing modes.
>
> Thanks.
> I'm currently in a class that is currently studying the MSP430 CPU.
> It is not the CPUX, but they use the same User's Guide (SLAU144).
> That said, I think I see what is going on. Looking at the Table for
> Format I Instruction Cycles and Lengths (SLAU144i, pg 150), it
> appears that you are looking at the source block. From my
> understanding, #0x1 is treated as an Rn source, not an x(Rn) source.
Is that stated or implied anywhere in the user manual because that's
what I couldn't find. Looking at sections 4.3.4 on Pg 124 it states that
+1 is R3 with an As value of 01. The example in section 4.3.4.1 on Pg
124 shows how the assembler would convert #1 to 0(R3).
Coupled with that, you can use the SR as a source or destination in Rn
mode, so it appeared to me that the modes were distinct.
The closest implication I found was in section 3.2.4 where it says
"Registers R2 and R3, used in the constant mode, cannot be addressed
explicitly; they act as source-only registers" but it's hardly a
definitive statement that the source addressing mode used is Rx.
> This would bring the cycle count to 4 before the application of the
> footnote. After the footnote, the total number of cycles would be 3
> (I am not 100% sure that I am applying it correctly though). Could it
> be that naken430 does not take the footnote into account?
I think my use of naken430 has thrown me (and this question) off
somewhat. It only supports the CPU core, not the CPUX core. When I look
at the instruction execution timings for the CPU "Rx,&EDE" is 4 cycles
without any footnotes.
So your statement that #0x1 is treated as an Rn source fits that too.
> How to get this answer by constructing the instruction by hand:
[...]
> All this was done by RTM.
Indeed, that's all written in the manual. And that's where I looked
first. But I haven't seen a definitive statement that says the constant
generators behave as register mode source for the purposes of execution
times. Perhaps it's just assumed that it's the only way they could work.
> Timothy Laufer Senior, Computer Science
> ________________________________ From: m...
> [m...] on behalf of David McMinn
> [d...@intelligentwellcontrols.com] Sent: Friday, September
> 14, 2012 3:51 AM To: MSP430 Subject: [msp430] Cycle counts for
> constant generator registers
>
> Hi,
>
> I am looking at counting the execution time of a piece of code and
> am unclear about the timings involved when the constant generator
> registers (R2 and R3) are used. I'm using the CPUX core in the 2619
> variant, but the small data model so most of the instructions are not
> extended.
>
> My particular confusion is about the following line (from IAR's
> listing):
>
> D2B30300 BIT.B #0x1, &0x3
>
> Pretty straightforward. #0x1 will be taken as 0(R3), destination is
> absolute address. Looking in the Format I instruction cycles and
> lengths I can see that the x(Rx),&TONI gives 6 cycles. I can reduce
> by 1 because it's a BIT instruction.
>
> I think I can reduce it again by 1 because the value for x is
> implicit in the instruction and not stored in memory. Is that
> correct? Disassembling using naken430 gives a cycle count of 4, and
> that's the only reason I can think that it is 2 cycles lower than
> what the user guide says for those addressing modes.
>
> Thanks.
Reply by ●September 14, 20122012-09-14
David the assembler shouldn't convert #1 to 0(R3) it has never done so
in the 13 years I've been using this micro.
The assembler uses register addressing mode. The best reference for this
is in the older SLAU010E chapter 5 which discusses registers and
operands. The section on emulated instructions is very clear:-
"The Constant Generator Registers allow ther emulation of several
instructions by other ones. The CPU is much simpler this way. Only 27
instructions are needed for the complete instruction set. For example
the Single Operand Instruction:
CLR dst
is emulated by the Double Operand Instruction with the same length:
MOV R3,dst
or equivalent
MOV #0,dst
where #0 is replaced by the assembler with R3 used with As = 00:"
It then continues:-
"*one word instruction
* no additional control operation or hardware within CPU
* register addressing mode for source: no extra fetch cycle for constants"
Thu s it does explicitly state that the constant generators behave as a
regiuster mode source.
I can send you a copy of thisd old document if you'd like to contact me
privately.
Al
On 15/09/2012 2:01 AM, David McMinn wrote:
> Hi Timothy,
>
>> I'm currently in a class that is currently studying the MSP430 CPU.
>> It is not the CPUX, but they use the same User's Guide (SLAU144).
>> That said, I think I see what is going on. Looking at the Table for
>> Format I Instruction Cycles and Lengths (SLAU144i, pg 150), it
>> appears that you are looking at the source block. From my
>> understanding, #0x1 is treated as an Rn source, not an x(Rn) source.
> Is that stated or implied anywhere in the user manual because that's
> what I couldn't find. Looking at sections 4.3.4 on Pg 124 it states that
> +1 is R3 with an As value of 01. The example in section 4.3.4.1 on Pg
> 124 shows how the assembler would convert #1 to 0(R3).
>
> Coupled with that, you can use the SR as a source or destination in Rn
> mode, so it appeared to me that the modes were distinct.
>
> The closest implication I found was in section 3.2.4 where it says
> "Registers R2 and R3, used in the constant mode, cannot be addressed
> explicitly; they act as source-only registers" but it's hardly a
> definitive statement that the source addressing mode used is Rx.
>
>> This would bring the cycle count to 4 before the application of the
>> footnote. After the footnote, the total number of cycles would be 3
>> (I am not 100% sure that I am applying it correctly though). Could it
>> be that naken430 does not take the footnote into account?
> I think my use of naken430 has thrown me (and this question) off
> somewhat. It only supports the CPU core, not the CPUX core. When I look
> at the instruction execution timings for the CPU "Rx,&EDE" is 4 cycles
> without any footnotes.
>
> So your statement that #0x1 is treated as an Rn source fits that too.
>
>> How to get this answer by constructing the instruction by hand:
> [...]
>
>> All this was done by RTM.
> Indeed, that's all written in the manual. And that's where I looked
> first. But I haven't seen a definitive statement that says the constant
> generators behave as register mode source for the purposes of execution
> times. Perhaps it's just assumed that it's the only way they could work.
>
>> Timothy Laufer Senior, Computer Science
>> ________________________________ From: m...
>> [m...] on behalf of David McMinn
>> [d...@intelligentwellcontrols.com] Sent: Friday, September
>> 14, 2012 3:51 AM To: MSP430 Subject: [msp430] Cycle counts for
>> constant generator registers
>>
>> Hi,
>>
>> I am looking at counting the execution time of a piece of code and
>> am unclear about the timings involved when the constant generator
>> registers (R2 and R3) are used. I'm using the CPUX core in the 2619
>> variant, but the small data model so most of the instructions are not
>> extended.
>>
>> My particular confusion is about the following line (from IAR's
>> listing):
>>
>> D2B30300 BIT.B #0x1, &0x3
>>
>> Pretty straightforward. #0x1 will be taken as 0(R3), destination is
>> absolute address. Looking in the Format I instruction cycles and
>> lengths I can see that the x(Rx),&TONI gives 6 cycles. I can reduce
>> by 1 because it's a BIT instruction.
>>
>> I think I can reduce it again by 1 because the value for x is
>> implicit in the instruction and not stored in memory. Is that
>> correct? Disassembling using naken430 gives a cycle count of 4, and
>> that's the only reason I can think that it is 2 cycles lower than
>> what the user guide says for those addressing modes.
>>
>> Thanks.
>
in the 13 years I've been using this micro.
The assembler uses register addressing mode. The best reference for this
is in the older SLAU010E chapter 5 which discusses registers and
operands. The section on emulated instructions is very clear:-
"The Constant Generator Registers allow ther emulation of several
instructions by other ones. The CPU is much simpler this way. Only 27
instructions are needed for the complete instruction set. For example
the Single Operand Instruction:
CLR dst
is emulated by the Double Operand Instruction with the same length:
MOV R3,dst
or equivalent
MOV #0,dst
where #0 is replaced by the assembler with R3 used with As = 00:"
It then continues:-
"*one word instruction
* no additional control operation or hardware within CPU
* register addressing mode for source: no extra fetch cycle for constants"
Thu s it does explicitly state that the constant generators behave as a
regiuster mode source.
I can send you a copy of thisd old document if you'd like to contact me
privately.
Al
On 15/09/2012 2:01 AM, David McMinn wrote:
> Hi Timothy,
>
>> I'm currently in a class that is currently studying the MSP430 CPU.
>> It is not the CPUX, but they use the same User's Guide (SLAU144).
>> That said, I think I see what is going on. Looking at the Table for
>> Format I Instruction Cycles and Lengths (SLAU144i, pg 150), it
>> appears that you are looking at the source block. From my
>> understanding, #0x1 is treated as an Rn source, not an x(Rn) source.
> Is that stated or implied anywhere in the user manual because that's
> what I couldn't find. Looking at sections 4.3.4 on Pg 124 it states that
> +1 is R3 with an As value of 01. The example in section 4.3.4.1 on Pg
> 124 shows how the assembler would convert #1 to 0(R3).
>
> Coupled with that, you can use the SR as a source or destination in Rn
> mode, so it appeared to me that the modes were distinct.
>
> The closest implication I found was in section 3.2.4 where it says
> "Registers R2 and R3, used in the constant mode, cannot be addressed
> explicitly; they act as source-only registers" but it's hardly a
> definitive statement that the source addressing mode used is Rx.
>
>> This would bring the cycle count to 4 before the application of the
>> footnote. After the footnote, the total number of cycles would be 3
>> (I am not 100% sure that I am applying it correctly though). Could it
>> be that naken430 does not take the footnote into account?
> I think my use of naken430 has thrown me (and this question) off
> somewhat. It only supports the CPU core, not the CPUX core. When I look
> at the instruction execution timings for the CPU "Rx,&EDE" is 4 cycles
> without any footnotes.
>
> So your statement that #0x1 is treated as an Rn source fits that too.
>
>> How to get this answer by constructing the instruction by hand:
> [...]
>
>> All this was done by RTM.
> Indeed, that's all written in the manual. And that's where I looked
> first. But I haven't seen a definitive statement that says the constant
> generators behave as register mode source for the purposes of execution
> times. Perhaps it's just assumed that it's the only way they could work.
>
>> Timothy Laufer Senior, Computer Science
>> ________________________________ From: m...
>> [m...] on behalf of David McMinn
>> [d...@intelligentwellcontrols.com] Sent: Friday, September
>> 14, 2012 3:51 AM To: MSP430 Subject: [msp430] Cycle counts for
>> constant generator registers
>>
>> Hi,
>>
>> I am looking at counting the execution time of a piece of code and
>> am unclear about the timings involved when the constant generator
>> registers (R2 and R3) are used. I'm using the CPUX core in the 2619
>> variant, but the small data model so most of the instructions are not
>> extended.
>>
>> My particular confusion is about the following line (from IAR's
>> listing):
>>
>> D2B30300 BIT.B #0x1, &0x3
>>
>> Pretty straightforward. #0x1 will be taken as 0(R3), destination is
>> absolute address. Looking in the Format I instruction cycles and
>> lengths I can see that the x(Rx),&TONI gives 6 cycles. I can reduce
>> by 1 because it's a BIT instruction.
>>
>> I think I can reduce it again by 1 because the value for x is
>> implicit in the instruction and not stored in memory. Is that
>> correct? Disassembling using naken430 gives a cycle count of 4, and
>> that's the only reason I can think that it is 2 cycles lower than
>> what the user guide says for those addressing modes.
>>
>> Thanks.
>
Reply by ●September 15, 20122012-09-15
In general, the MSP430 instruction cycle and length are specified in Sections
3.4.4.1 through 3.4.4.4 of that user's guide. However, if and when the
"constant generator" is used to generate the #N in Table 3-16 of Section
3.4.4.4, the actual cycle and length are both 1 less than what are shown there.
This is not implicitly pointed out. Instead, it is implied in Section 3.2.4 by
stating:
The constant generator advantages are:
No special instructions required
No additional code word for the six constants
No code memory access required to retrieve the constant
I have tried to verify these assertions and they seem correct in actual hardware.
One thing through, the assembler does not "automatically" use the constant generator in all cases due to a very obscure reason.
--- In m..., David McMinn wrote:
>
> Hi Timothy,
>
> > I'm currently in a class that is currently studying the MSP430 CPU.
> > It is not the CPUX, but they use the same User's Guide (SLAU144).
> > That said, I think I see what is going on. Looking at the Table for
> > Format I Instruction Cycles and Lengths (SLAU144i, pg 150), it
> > appears that you are looking at the source block. From my
> > understanding, #0x1 is treated as an Rn source, not an x(Rn) source.
>
> Is that stated or implied anywhere in the user manual because that's
> what I couldn't find. Looking at sections 4.3.4 on Pg 124 it states that
> +1 is R3 with an As value of 01. The example in section 4.3.4.1 on Pg
> 124 shows how the assembler would convert #1 to 0(R3).
>
> Coupled with that, you can use the SR as a source or destination in Rn
> mode, so it appeared to me that the modes were distinct.
>
> The closest implication I found was in section 3.2.4 where it says
> "Registers R2 and R3, used in the constant mode, cannot be addressed
> explicitly; they act as source-only registers" but it's hardly a
> definitive statement that the source addressing mode used is Rx.
>
> > This would bring the cycle count to 4 before the application of the
> > footnote. After the footnote, the total number of cycles would be 3
> > (I am not 100% sure that I am applying it correctly though). Could it
> > be that naken430 does not take the footnote into account?
>
> I think my use of naken430 has thrown me (and this question) off
> somewhat. It only supports the CPU core, not the CPUX core. When I look
> at the instruction execution timings for the CPU "Rx,&EDE" is 4 cycles
> without any footnotes.
>
> So your statement that #0x1 is treated as an Rn source fits that too.
>
> > How to get this answer by constructing the instruction by hand:
>
> [...]
>
> > All this was done by RTM.
>
> Indeed, that's all written in the manual. And that's where I looked
> first. But I haven't seen a definitive statement that says the constant
> generators behave as register mode source for the purposes of execution
> times. Perhaps it's just assumed that it's the only way they could work.
>
> > Timothy Laufer Senior, Computer Science
> > ________________________________ From: m...
> > [m...] on behalf of David McMinn
> > [david.mcminn@...] Sent: Friday, September
> > 14, 2012 3:51 AM To: MSP430 Subject: [msp430] Cycle counts for
> > constant generator registers
> >
> >
> >
> > Hi,
> >
> > I am looking at counting the execution time of a piece of code and
> > am unclear about the timings involved when the constant generator
> > registers (R2 and R3) are used. I'm using the CPUX core in the 2619
> > variant, but the small data model so most of the instructions are not
> > extended.
> >
> > My particular confusion is about the following line (from IAR's
> > listing):
> >
> > D2B30300 BIT.B #0x1, &0x3
> >
> > Pretty straightforward. #0x1 will be taken as 0(R3), destination is
> > absolute address. Looking in the Format I instruction cycles and
> > lengths I can see that the x(Rx),&TONI gives 6 cycles. I can reduce
> > by 1 because it's a BIT instruction.
> >
> > I think I can reduce it again by 1 because the value for x is
> > implicit in the instruction and not stored in memory. Is that
> > correct? Disassembling using naken430 gives a cycle count of 4, and
> > that's the only reason I can think that it is 2 cycles lower than
> > what the user guide says for those addressing modes.
> >
> > Thanks.
>
The constant generator advantages are:
No special instructions required
No additional code word for the six constants
No code memory access required to retrieve the constant
I have tried to verify these assertions and they seem correct in actual hardware.
One thing through, the assembler does not "automatically" use the constant generator in all cases due to a very obscure reason.
--- In m..., David McMinn wrote:
>
> Hi Timothy,
>
> > I'm currently in a class that is currently studying the MSP430 CPU.
> > It is not the CPUX, but they use the same User's Guide (SLAU144).
> > That said, I think I see what is going on. Looking at the Table for
> > Format I Instruction Cycles and Lengths (SLAU144i, pg 150), it
> > appears that you are looking at the source block. From my
> > understanding, #0x1 is treated as an Rn source, not an x(Rn) source.
>
> Is that stated or implied anywhere in the user manual because that's
> what I couldn't find. Looking at sections 4.3.4 on Pg 124 it states that
> +1 is R3 with an As value of 01. The example in section 4.3.4.1 on Pg
> 124 shows how the assembler would convert #1 to 0(R3).
>
> Coupled with that, you can use the SR as a source or destination in Rn
> mode, so it appeared to me that the modes were distinct.
>
> The closest implication I found was in section 3.2.4 where it says
> "Registers R2 and R3, used in the constant mode, cannot be addressed
> explicitly; they act as source-only registers" but it's hardly a
> definitive statement that the source addressing mode used is Rx.
>
> > This would bring the cycle count to 4 before the application of the
> > footnote. After the footnote, the total number of cycles would be 3
> > (I am not 100% sure that I am applying it correctly though). Could it
> > be that naken430 does not take the footnote into account?
>
> I think my use of naken430 has thrown me (and this question) off
> somewhat. It only supports the CPU core, not the CPUX core. When I look
> at the instruction execution timings for the CPU "Rx,&EDE" is 4 cycles
> without any footnotes.
>
> So your statement that #0x1 is treated as an Rn source fits that too.
>
> > How to get this answer by constructing the instruction by hand:
>
> [...]
>
> > All this was done by RTM.
>
> Indeed, that's all written in the manual. And that's where I looked
> first. But I haven't seen a definitive statement that says the constant
> generators behave as register mode source for the purposes of execution
> times. Perhaps it's just assumed that it's the only way they could work.
>
> > Timothy Laufer Senior, Computer Science
> > ________________________________ From: m...
> > [m...] on behalf of David McMinn
> > [david.mcminn@...] Sent: Friday, September
> > 14, 2012 3:51 AM To: MSP430 Subject: [msp430] Cycle counts for
> > constant generator registers
> >
> >
> >
> > Hi,
> >
> > I am looking at counting the execution time of a piece of code and
> > am unclear about the timings involved when the constant generator
> > registers (R2 and R3) are used. I'm using the CPUX core in the 2619
> > variant, but the small data model so most of the instructions are not
> > extended.
> >
> > My particular confusion is about the following line (from IAR's
> > listing):
> >
> > D2B30300 BIT.B #0x1, &0x3
> >
> > Pretty straightforward. #0x1 will be taken as 0(R3), destination is
> > absolute address. Looking in the Format I instruction cycles and
> > lengths I can see that the x(Rx),&TONI gives 6 cycles. I can reduce
> > by 1 because it's a BIT instruction.
> >
> > I think I can reduce it again by 1 because the value for x is
> > implicit in the instruction and not stored in memory. Is that
> > correct? Disassembling using naken430 gives a cycle count of 4, and
> > that's the only reason I can think that it is 2 cycles lower than
> > what the user guide says for those addressing modes.
> >
> > Thanks.
>
Reply by ●September 25, 20122012-09-25
Hi OCY, Onestone and Timothy,
I'm back after a week away so I'll make this short. Thanks for all your insights and explanations, and pointers to the explanations. I'm happy that three people have independantly said the same thing so I'll go with what you've all said - that using the constant generator is a Rn source operation with regards to cycle timing and not one of the more complex modes.
Cheers.
I'm back after a week away so I'll make this short. Thanks for all your insights and explanations, and pointers to the explanations. I'm happy that three people have independantly said the same thing so I'll go with what you've all said - that using the constant generator is a Rn source operation with regards to cycle timing and not one of the more complex modes.
Cheers.
