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Caches on non-FRAM MSP430 parts?

Started by Ben Ransford October 30, 2012
Hello,

In search of various MSP430 architectural details for an academic research
project, I've been unable to find information on whether MSP430
microcontrollers use caches. According to
slaa498,
the FRAM parts use an instruction cache in front of the FRAM because the
MCU's clock rate can be triple the FRAM's, but I can't find any information
on the non-FRAM parts.

There also doesn't seem to be much publicly available information on the
MSP430's instruction pipeline, if there is one, but that's a separate
matter.

Rumor has it that support engineers are forced to divulge architectural
details from time to time in order to debug customers' corner cases. Does
that information stay secret?

I would be grateful for any information in this vein, especially pointers
to TI publications.

-ben


Beginning Microcontrollers with the MSP430

Ben Ransford :

> Hello,
>
> In search of various MSP430 architectural details for an academic research
> project, I've been unable to find information on whether MSP430
> microcontrollers use caches. According to
> slaa498,
> the FRAM parts use an instruction cache in front of the FRAM because the
> MCU's clock rate can be triple the FRAM's, but I can't find any information
> on the non-FRAM parts.
>
> There also doesn't seem to be much publicly available information on the
> MSP430's instruction pipeline, if there is one, but that's a separate
> matter.

Afaik there is no instruction pipeline in the MSP430F parts. They use a 32bit
FLASH data bus to achieve the speed in the 16 bit controllers (read 2 words
at once).

M.

On 01.11.2012 10:23, Matthias Weingart wrote:
:
> Afaik there is no instruction pipeline in the MSP430F parts. They use a
> 32bit

I guess there is one: http://lmgtfy.com/?q=msp430+pipeline (although
this is not a proof...). If one checks the errata documents, some of
the CPUx errata seem to be caused by bugs in the pipeline.

Hardy