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Changing the frequency of MCLK on MSP430FG4618

Started by kahunwa November 9, 2012
Hello! I am trying to to change the frequency of MCLK (to 8.0 MHz) on the MSP430FG4618. But I cant get it to exactly to 8.0 MHz. According to my calculations, N should be 121, but am having to hard time figuring it out. Here is my code:

#include

void main (void)
{
WDTCTL = WDTHOLD | WDTPW; //Stop Watchdog Timer

P1DIR |= BIT1; //set port pin P1.1 to output direction
P1SEL |= BIT1; //peripheral module function for port pin P1.1 & P1.5

SCFI0 |= FN_2; //Sets fDCO operating range: 1.4MHz to 12MHz
SCFQCTL |= SCFQ_4M; //fMCLK = 128*fACLK
SCFI0 |= FLLD_2; //Multiply by 2
FLL_CTL0 |= DCOPLUS; // fDC0CLK = D(N + 1) * fACLK

// D=2 (default) N8 fACLK = 32.768 kHz

// ==> MCLK measured frequency is approximately 8.47 MHz

} /* end main function */

Beginning Microcontrollers with the MSP430

kahunwa wrote:
> Hello! I am trying to to change the frequency of MCLK (to 8.0 MHz) on the MSP430FG4618. But I cant get it to exactly to 8.0 MHz. According to my calculations, N should be 121, but am having to hard time figuring it out. Here is my code:
>
> #include
>
> void main (void)
> {
> WDTCTL = WDTHOLD | WDTPW; //Stop Watchdog Timer
>
> P1DIR |= BIT1; //set port pin P1.1 to output direction
> P1SEL |= BIT1; //peripheral module function for port pin P1.1 & P1.5
>
> SCFI0 |= FN_2; //Sets fDCO operating range: 1.4MHz to 12MHz
> SCFQCTL |= SCFQ_4M; //fMCLK = 128*fACLK
> SCFI0 |= FLLD_2; //Multiply by 2
> FLL_CTL0 |= DCOPLUS; // fDC0CLK = D(N + 1) * fACLK
>
> // D=2 (default) N8 fACLK = 32.768 kHz
>
>
> // ==> MCLK measured frequency is approximately 8.47 MHz
>
>
> } /* end main function */
>

Pretty much looks like a class assignment gone bad. Best you can do on a
simple board is phase lock to a watch crystal. Try a Google search on that.

Best, Dan.
--
"If they can get you asking the wrong questions, they dont
have to worry about answers."

-- Thomas Pynchon