HCS12, XCLKS = ? for External Square Wave clock?

Started by varneybob October 30, 2002
I cannot determine what value to set XCLKS (0 or 1) on the HCS12 for
use with an external square-wave clock source.

The V2.13 HCS12 Device User Guide, Section 2.3.13 states:

If [XCLKS] is logic *low* the EXTAL pin is configured fro an
external clock drive.

But the V2.07 CRG Block User Guide shows in Figure 2-3, and in Table
2-1, that:

XCLK is logic *high* for external clock drive.

Anybody know for sure what to set XCLKS to?



Bob,

For all currently available HCS12 parts EXCEPT the MC9S12H256 XCLKS = 0
selects an external clock and/or (in newer parts/mask sets) a Pierce
oscillator configuration.

Regards,
Gordon

--
===============================================================
Gordon Doughman Ph: 937-438-6811
Motorola Semiconductor Fax: 937-434-7457
Field Applications Engineer Pager: 800-759-8352 Pin: 1304089
Suite 175
3131 Newmark Drive
Miamisburg, OH 45342

Check out my HC12 book at:
http://www.rtcgroup.com/books/ varneybob wrote:

> I cannot determine what value to set XCLKS (0 or 1) on the HCS12 for
> use with an external square-wave clock source.
>
> The V2.13 HCS12 Device User Guide, Section 2.3.13 states:
>
> If [XCLKS] is logic *low* the EXTAL pin is configured fro an
> external clock drive.
>
> But the V2.07 CRG Block User Guide shows in Figure 2-3, and in Table
> 2-1, that:
>
> XCLK is logic *high* for external clock drive.
>
> Anybody know for sure what to set XCLKS to? > -------------------- >
> ">http://docs.yahoo.com/info/terms/





XCLKS (PE7) should be driven low during reset to configure for an external
clock generator or an external pierce crystal configuration.

For an external Colpitts crystal configuration it should be driven high
during Reset (or left un-driven to be pulled high using the enabled
internal pull up on PE7).

Doron
Nohau Corporation
HC12 In-Circuit Emulators
www.nohau.com At 06:52 PM 10/30/2002 +0000, you wrote:
>I cannot determine what value to set XCLKS (0 or 1) on the HCS12 for
>use with an external square-wave clock source.
>
>The V2.13 HCS12 Device User Guide, Section 2.3.13 states:
>
> If [XCLKS] is logic *low* the EXTAL pin is configured fro an
>external clock drive.
>
>But the V2.07 CRG Block User Guide shows in Figure 2-3, and in Table
>2-1, that:
>
> XCLK is logic *high* for external clock drive.
>
>Anybody know for sure what to set XCLKS to?