Fwd: Very basic RTL synthesis question by a hobbyist

Started by Aidan Keady in FPGA-CPU4 years ago 1 reply

Hi, This has ended up being quite rambling - hope it's of some use! - the short version is look at the espresso logic optimiser [1] and book...

Hi, This has ended up being quite rambling - hope it's of some use! - the short version is look at the espresso logic optimiser [1] and book [2] and possibly see how the priority comes down to just combinational logic like the other examples. I think you're right that optimisation usually happens before the logic is mapped to a particular target library. Something like the espresso [1...


Beginning with FGPA

Started by "reu...@bellsouth.net" in FPGA-CPU4 years ago 24 replies

Hello, I am a senior in high school and have been studying ALU and CPU design independently. I have just read "Bebop Bytes Back" and have just...

Hello, I am a senior in high school and have been studying ALU and CPU design independently. I have just read "Bebop Bytes Back" and have just purchased a book titled "HDL Chip Design". Starting with FPGA's was recommended to me, but I was overwhelmed after trying to choose a board. Would anyone be able to recommend a board for a beginner, one with a generous amount of tools (switches, 7-segm...


FYI: LogicProbe on Opencores

Started by Hellwig Geisse in FPGA-CPU4 years ago 2 replies

Hi all, I didn't get any mail from this list for more than half a year, and I wonder if anyone is listening here at all... :-) Anyway, I...

Hi all, I didn't get any mail from this list for more than half a year, and I wonder if anyone is listening here at all... :-) Anyway, I finally uploaded an old project to OpenCores: http://opencores.org/project,logicprobe Merry Christmas and a Happy New Year! Hellwig ------------------------------------ To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a b...


fpgasm - a low-level design language for Xilinx FPGAs

Started by "arm7.developer" in FPGA-CPU5 years ago

Hello, I would like to present to you an alternative to Verilog and VHDL - FPGA Assembler. I've been fiddling with FPGAs for a while. ...

Hello, I would like to present to you an alternative to Verilog and VHDL - FPGA Assembler. I've been fiddling with FPGAs for a while. I've been working on some open source tools to make FPGA work not totally unpleasant. fpgasm is to Verilog is what assembly language is to C++. With fewer than 10 reserved words, you can actually start hacking in minutes. Anyway, I hope you get a chanc...


Using DDR RAM

Started by rtstofer in FPGA-CPU6 years ago 43 replies

I bought a Digilent Spartan 3E Starter Board and it comes with 32M x 16 of DDR RAM. They don't provide a controller core. So I started over at...

I bought a Digilent Spartan 3E Starter Board and it comes with 32M x 16 of DDR RAM. They don't provide a controller core. So I started over at OpenCores and downloaded a DDR core but I haven't even begun to study it. Instead I went to the datasheet... I notice that it takes 2 clocks to get the first word from memory. Then I can get a word every 1/2 clock. It's that initial 2 clocks that ...


step by step cpu design using altera fpga

Started by SNFEDOGAN in FPGA-CPU7 years ago 14 replies

Hi everyone i am quite new to fpga, cpu design and group as well ... I am sure its asked zillion of times in this group but I need urgent...

Hi everyone i am quite new to fpga, cpu design and group as well ... I am sure its asked zillion of times in this group but I need urgent help is there any book, internet page, tutorial etc, which starts from scratch and goes up to design a simple cpu, including features such as, registers, in. sets, alu etc.... I am trying to prepare "Computer Architecture" class for computer e


FPGA to ARM7 shared memory concept via wishbone.

Started by djam...@gmail.com in FPGA-CPU7 years ago 5 replies

Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration...

Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration device for cyclone3) -- an LPC2468 ARM processor (running uLinux), -- a 16M Synchronous DRAM (connected to FPGA and ARM) -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to...


Implementation of LRU algo in verilog

Started by ruchi_rastogi25 in FPGA-CPU8 years ago 6 replies

Hi all, I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is...

Hi all, I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is the optimal way of implementating LRU(Least Recently Used)algo in Hardware. Thanks, Ruchi ------------------------------------ To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com ...


Design mini cpu?

Started by potxoka3a in FPGA-CPU9 years ago 5 replies

hi I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an FPGA= with VHDL, analyzing and changing a few signs of a data bus...

hi I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an FPGA= with VHDL, analyzing and changing a few signs of a data bus of 20 signals = (transceiver). These signals often change protocol, as the team changes dur= ing the design in VHDL I changed 2 times. To avoid having to always fpga programming, thought if there was any way to= change the interpretation of these s...


ARM7 - FPGA

Started by sumana0281 in FPGA-CPU9 years ago 2 replies

Sir, I am doing a project on memory accelerator for ARM7TDMI. I have coded memory accelerator in VHDL. The memory used is a flash. I have LPC2129...

Sir, I am doing a project on memory accelerator for ARM7TDMI. I have coded memory accelerator in VHDL. The memory used is a flash. I have LPC2129 Arm processor with me. Does altera kit support for FPGA as well as ARM processor? or suggest any other option. kindly guide me. regards and thanx in advance sumana ------------------------------------ To post a message, send it to: f...@yahoogro...


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