9s12d64 -External memory access

Started by imtiyazfmn September 8, 2011
Hello,
I am going t use 9s12d64 for my older design with replacing this.In older design MC68HC11 was used.on that design an FPGA used on 0x8000 to 0x803f adress.So now i wanted to use same adress for an FPGA so is it possible in 9s12d64 controller?
Since i have read that 0x8000 to 0xBFFF is used for program memory using page window.And insight of micro internal flash is available in this location so i am thinking that i can not used for external FPGA access.
So please anyone can suggest that can i used that location for external FPGA access for read and write? if yes please give me setting of internal registor to disble internal flash on that location ?
Also please suggest linker file section to difine it external Read write memory in cosmic compiler linker file (lkf file).

S12D multiplexed external memory interface is not as easy to use as it was
on HC11. What else do you plan to interface with ext.memory bus? If none,
then just bitbang those data, address and CS lines. S12D bus clock is >6
times faster than HC11 with 16MHz crystal. If indeed you need to access a
lot of address space, then better choose S12XD, S12XA or S12XE MCU's. Of
course you may dislike the need to choose only >4 pins packages. But
interfacing to S12X memory bus is easy, both codewise and HW-wise.

0x8000 address can be used, but then you will be either limited to 32kB of
nonbanked program memory, or not access your FPGA from banked routines.

Can't help you with Cosmic.

Edward

----- Original Message -----
From: "imtiyazfmn"
To: <6...>
Sent: Thursday, September 08, 2011 10:38 PM
Subject: [68HC12] 9s12d64 -External memory access
> Hello,
> I am going t use 9s12d64 for my older design with replacing this.In older
> design MC68HC11 was used.on that design an FPGA used on 0x8000 to 0x803f
> adress.So now i wanted to use same adress for an FPGA so is it possible in
> 9s12d64 controller?
> Since i have read that 0x8000 to 0xBFFF is used for program memory using
> page window.And insight of micro internal flash is available in this
> location so i am thinking that i can not used for external FPGA access.
> So please anyone can suggest that can i used that location for external
> FPGA access for read and write? if yes please give me setting of internal
> registor to disble internal flash on that location ?
> Also please suggest linker file section to difine it external Read write
> memory in cosmic compiler linker file (lkf file).
>
>
Thanks for reply..
Actually we will use only FPGA on external bus and my program size is also less then 5k and we don't want to change in firmware (like bitbang ) because decoding logic is insight of FPGA and we will 10MHZ external clock feed to micro with disable internal PLL .
So please suggest me how can i disable flash on ox8000 to 0xBFFF adress location?
If any other thing that i need to confirm please suggest?

--- In 6..., "Edvardas" wrote:
>
> S12D multiplexed external memory interface is not as easy to use as it was
> on HC11. What else do you plan to interface with ext.memory bus? If none,
> then just bitbang those data, address and CS lines. S12D bus clock is >6
> times faster than HC11 with 16MHz crystal. If indeed you need to access a
> lot of address space, then better choose S12XD, S12XA or S12XE MCU's. Of
> course you may dislike the need to choose only >4 pins packages. But
> interfacing to S12X memory bus is easy, both codewise and HW-wise.
>
> 0x8000 address can be used, but then you will be either limited to 32kB of
> nonbanked program memory, or not access your FPGA from banked routines.
>
> Can't help you with Cosmic.
>
> Edward
>
> ----- Original Message -----
> From: "imtiyazfmn"
> To: <6...>
> Sent: Thursday, September 08, 2011 10:38 PM
> Subject: [68HC12] 9s12d64 -External memory access
> > Hello,
> > I am going t use 9s12d64 for my older design with replacing this.In older
> > design MC68HC11 was used.on that design an FPGA used on 0x8000 to 0x803f
> > adress.So now i wanted to use same adress for an FPGA so is it possible in
> > 9s12d64 controller?
> > Since i have read that 0x8000 to 0xBFFF is used for program memory using
> > page window.And insight of micro internal flash is available in this
> > location so i am thinking that i can not used for external FPGA access.
> > So please anyone can suggest that can i used that location for external
> > FPGA access for read and write? if yes please give me setting of internal
> > registor to disble internal flash on that location ?
> > Also please suggest linker file section to difine it external Read write
> > memory in cosmic compiler linker file (lkf file).
> >
> >
> >
> >
> >
> >
Single external device with few addresses? It doesn't make sense to use
external bus on S12D. Bitbanging you could use less pins for the same task.

Since you are going to feed external clock to S12D, don't omit that Vhi of
this signal should be not higher than Vddpll (~2.5V).

You don't need to disable flash on 0x8000, you just need to set PPAGE
register to any value from 0 to 0x3B. In expanded mode pages 0x3C-0x3F will
map internal D64 flash to 0x8000, pages 0-0x3B - external memory.

Edward
----- Original Message -----
From: "imtiyazfmn"
To: <6...>
Sent: Friday, September 09, 2011 4:44 PM
Subject: [68HC12] Re: 9s12d64 -External memory access
> Thanks for reply..
> Actually we will use only FPGA on external bus and my program size is also
> less then 5k and we don't want to change in firmware (like bitbang )
> because decoding logic is insight of FPGA and we will 10MHZ external clock
> feed to micro with disable internal PLL .
> So please suggest me how can i disable flash on ox8000 to 0xBFFF adress
> location?
> If any other thing that i need to confirm please suggest?
>
> --- In 6..., "Edvardas" wrote:
>>
>> S12D multiplexed external memory interface is not as easy to use as it
>> was
>> on HC11. What else do you plan to interface with ext.memory bus? If none,
>> then just bitbang those data, address and CS lines. S12D bus clock is >6
>> times faster than HC11 with 16MHz crystal. If indeed you need to access a
>> lot of address space, then better choose S12XD, S12XA or S12XE MCU's. Of
>> course you may dislike the need to choose only >4 pins packages. But
>> interfacing to S12X memory bus is easy, both codewise and HW-wise.
>>
>> 0x8000 address can be used, but then you will be either limited to 32kB
>> of
>> nonbanked program memory, or not access your FPGA from banked routines.
>>
>> Can't help you with Cosmic.
>>
>> Edward
>>
>> ----- Original Message -----
>> From: "imtiyazfmn"
>> To: <6...>
>> Sent: Thursday, September 08, 2011 10:38 PM
>> Subject: [68HC12] 9s12d64 -External memory access
>> > Hello,
>> > I am going t use 9s12d64 for my older design with replacing this.In
>> > older
>> > design MC68HC11 was used.on that design an FPGA used on 0x8000 to
>> > 0x803f
>> > adress.So now i wanted to use same adress for an FPGA so is it possible
>> > in
>> > 9s12d64 controller?
>> > Since i have read that 0x8000 to 0xBFFF is used for program memory
>> > using
>> > page window.And insight of micro internal flash is available in this
>> > location so i am thinking that i can not used for external FPGA access.
>> > So please anyone can suggest that can i used that location for external
>> > FPGA access for read and write? if yes please give me setting of
>> > internal
>> > registor to disble internal flash on that location ?
>> > Also please suggest linker file section to difine it external Read
>> > write
>> > memory in cosmic compiler linker file (lkf file).
>> >
>> >
>> >
>> >
>> >
>> >
Can you please suggest me that how can i change PPAGE in my code memory for access external memory?
And also please suggest that how to set PPAGE for 1st time when my device is power on/Reset because its default PPAGE VALUE is zero at reset and my fixed flash is on 3F PPAGE value ? will it automatically set at reset vector location or what?

Imtiyaz

--- In 6..., "Edvard Karpicz" wrote:
>
> Single external device with few addresses? It doesn't make sense to use
> external bus on S12D. Bitbanging you could use less pins for the same task.
>
> Since you are going to feed external clock to S12D, don't omit that Vhi of
> this signal should be not higher than Vddpll (~2.5V).
>
> You don't need to disable flash on 0x8000, you just need to set PPAGE
> register to any value from 0 to 0x3B. In expanded mode pages 0x3C-0x3F will
> map internal D64 flash to 0x8000, pages 0-0x3B - external memory.
>
> Edward
> ----- Original Message -----
> From: "imtiyazfmn"
> To: <6...>
> Sent: Friday, September 09, 2011 4:44 PM
> Subject: [68HC12] Re: 9s12d64 -External memory access
> > Thanks for reply..
> > Actually we will use only FPGA on external bus and my program size is also
> > less then 5k and we don't want to change in firmware (like bitbang )
> > because decoding logic is insight of FPGA and we will 10MHZ external clock
> > feed to micro with disable internal PLL .
> > So please suggest me how can i disable flash on ox8000 to 0xBFFF adress
> > location?
> > If any other thing that i need to confirm please suggest?
> >
> > --- In 6..., "Edvardas" wrote:
> >>
> >> S12D multiplexed external memory interface is not as easy to use as it
> >> was
> >> on HC11. What else do you plan to interface with ext.memory bus? If none,
> >> then just bitbang those data, address and CS lines. S12D bus clock is >6
> >> times faster than HC11 with 16MHz crystal. If indeed you need to access a
> >> lot of address space, then better choose S12XD, S12XA or S12XE MCU's. Of
> >> course you may dislike the need to choose only >4 pins packages. But
> >> interfacing to S12X memory bus is easy, both codewise and HW-wise.
> >>
> >> 0x8000 address can be used, but then you will be either limited to 32kB
> >> of
> >> nonbanked program memory, or not access your FPGA from banked routines.
> >>
> >> Can't help you with Cosmic.
> >>
> >> Edward
> >>
> >> ----- Original Message -----
> >> From: "imtiyazfmn"
> >> To: <6...>
> >> Sent: Thursday, September 08, 2011 10:38 PM
> >> Subject: [68HC12] 9s12d64 -External memory access
> >>
> >>
> >> > Hello,
> >> > I am going t use 9s12d64 for my older design with replacing this.In
> >> > older
> >> > design MC68HC11 was used.on that design an FPGA used on 0x8000 to
> >> > 0x803f
> >> > adress.So now i wanted to use same adress for an FPGA so is it possible
> >> > in
> >> > 9s12d64 controller?
> >> > Since i have read that 0x8000 to 0xBFFF is used for program memory
> >> > using
> >> > page window.And insight of micro internal flash is available in this
> >> > location so i am thinking that i can not used for external FPGA access.
> >> > So please anyone can suggest that can i used that location for external
> >> > FPGA access for read and write? if yes please give me setting of
> >> > internal
> >> > registor to disble internal flash on that location ?
> >> > Also please suggest linker file section to difine it external Read
> >> > write
> >> > memory in cosmic compiler linker file (lkf file).
> >> >
> >> >
> >> >
> >> >
> >> >
> >> >
Default PPAGE is 0? That's good news for you, you don't need to do anything.
Your FPGA should be accessible at 0x8000 out of reset in normal expanded
mode.

You said you don't need a lot of flash. So 32kB of nonbanked flash
(0x4000..0x7FFF and 0xC000..0xFFFF) should suffice, right? So no need to
write to PPAGE register.

Edward

----- Original Message -----
From: "imtiyazfmn"
To: <6...>
Sent: Tuesday, September 13, 2011 4:38 PM
Subject: [68HC12] Re: 9s12d64 -External memory access
> Can you please suggest me that how can i change PPAGE in my code memory
> for access external memory?
> And also please suggest that how to set PPAGE for 1st time when my device
> is power on/Reset because its default PPAGE VALUE is zero at reset and my
> fixed flash is on 3F PPAGE value ? will it automatically set at reset
> vector location or what?
>
> Imtiyaz
> --- In 6..., "Edvard Karpicz" wrote:
>>
>> Single external device with few addresses? It doesn't make sense to use
>> external bus on S12D. Bitbanging you could use less pins for the same
>> task.
>>
>> Since you are going to feed external clock to S12D, don't omit that Vhi
>> of
>> this signal should be not higher than Vddpll (~2.5V).
>>
>> You don't need to disable flash on 0x8000, you just need to set PPAGE
>> register to any value from 0 to 0x3B. In expanded mode pages 0x3C-0x3F
>> will
>> map internal D64 flash to 0x8000, pages 0-0x3B - external memory.
>>
>> Edward
>> ----- Original Message -----
>> From: "imtiyazfmn"
>> To: <6...>
>> Sent: Friday, September 09, 2011 4:44 PM
>> Subject: [68HC12] Re: 9s12d64 -External memory access
>> > Thanks for reply..
>> > Actually we will use only FPGA on external bus and my program size is
>> > also
>> > less then 5k and we don't want to change in firmware (like bitbang )
>> > because decoding logic is insight of FPGA and we will 10MHZ external
>> > clock
>> > feed to micro with disable internal PLL .
>> > So please suggest me how can i disable flash on ox8000 to 0xBFFF adress
>> > location?
>> > If any other thing that i need to confirm please suggest?
>> >
>> > --- In 6..., "Edvardas" wrote:
>> >>
>> >> S12D multiplexed external memory interface is not as easy to use as it
>> >> was
>> >> on HC11. What else do you plan to interface with ext.memory bus? If
>> >> none,
>> >> then just bitbang those data, address and CS lines. S12D bus clock is
>> >> >6
>> >> times faster than HC11 with 16MHz crystal. If indeed you need to
>> >> access a
>> >> lot of address space, then better choose S12XD, S12XA or S12XE MCU's.
>> >> Of
>> >> course you may dislike the need to choose only >4 pins packages.
>> >> But
>> >> interfacing to S12X memory bus is easy, both codewise and HW-wise.
>> >>
>> >> 0x8000 address can be used, but then you will be either limited to
>> >> 32kB
>> >> of
>> >> nonbanked program memory, or not access your FPGA from banked
>> >> routines.
>> >>
>> >> Can't help you with Cosmic.
>> >>
>> >> Edward
>> >>
>> >> ----- Original Message -----
>> >> From: "imtiyazfmn"
>> >> To: <6...>
>> >> Sent: Thursday, September 08, 2011 10:38 PM
>> >> Subject: [68HC12] 9s12d64 -External memory access
>> >>
>> >>
>> >> > Hello,
>> >> > I am going t use 9s12d64 for my older design with replacing this.In
>> >> > older
>> >> > design MC68HC11 was used.on that design an FPGA used on 0x8000 to
>> >> > 0x803f
>> >> > adress.So now i wanted to use same adress for an FPGA so is it
>> >> > possible
>> >> > in
>> >> > 9s12d64 controller?
>> >> > Since i have read that 0x8000 to 0xBFFF is used for program memory
>> >> > using
>> >> > page window.And insight of micro internal flash is available in this
>> >> > location so i am thinking that i can not used for external FPGA
>> >> > access.
>> >> > So please anyone can suggest that can i used that location for
>> >> > external
>> >> > FPGA access for read and write? if yes please give me setting of
>> >> > internal
>> >> > registor to disble internal flash on that location ?
>> >> > Also please suggest linker file section to difine it external Read
>> >> > write
>> >> > memory in cosmic compiler linker file (lkf file).
>> >> >
>> >> >
>> >> >
>> >> >
>> >> >
>> >> >
Hello,
Please help me in this regards..
Now i have started testing of my new design.the problem is when i switched my micro in Expanded wide mode from single chip mode ,there are nothing exwctutuin inside.Eclk is at 5mhz on 10mhz crystal.but i have set ECLK as a external access not free running.And i am accessing external adress contineus in loop but nothing can seen on adress line also i can not see r/w pulse as low...for your ref code is as follow with s19 file.

void main(void)
{
/* asserted when energize asserted (sys mon) */

/*
Protect the configuration register but allow changes to
rest of EEPROM. This must be done in the first 64 clock
cycles after reset.
*/
/*BlockProtectReg = PTCON;*/

/*
Enable the internal oscillator to generate the programming
voltage for the EEPROM. This is required because the 'E'
frequency is less than 2 Mhz.
*/
/*OptionReg = CSEL;*/
MODE=0xE0; /* EXPANDED WIDE MODE*//* 0xC0 FOR NARROW EXA.*/
INTCR=0x00;/*External IRQ Disable */
PLLCTL=0xB1; /*PLL off */
INITRM=0x10; /* remap RAM to 0x1000 */
INITEE=0x09; /*remap EEPROM to 0x800 and initialize*/
PEAR=0x04; /* R/W Enable on pin out of micro */
EBICTL; /*eclk as a external */
MISC=0x07; /* ECLK is stretched to one cycle,onchip flash/rom enable and 0x4000 to 0x7fff is used as external memory not flash memory */
for(i=0;i<512;i++) /* delay */
flag=0;
Repeat:
for(i=0;i<2;i++)
{
if(flag==0)
StatToSlink=0x2aaa;
else
RdWrTest=0x5555;

}
if(flag==0)
flag=1;
else
flag=0;
goto Repeat;
}

S19 FILE

S03B0000433A5C496D746979617A5C436F6E742E456E675C5265736F6C7665725C5331325C746573745F636F64655C546573745F533132442E483132C8
S123FF8000000000000000000000000000000000000000000000000000000000000000005D
S115FFA0000000000000C0090000000000000000C000C2
S123C00087CF1FFF16C00D20FEC75B1E0BC6E05B0BC75B1EC6B15B3AC6105B10C6095B1287
S123C020C6045B0AC6015B0EC6075B1387C77C100287C77C1000FD1002027D10028D02007D
S123C0402DEF87C77C1002FC10002608CC2AAA7C80002006CC55557C8006FD1002027D10D2
S11AC060028D00022DE1FC10002605CC0001200287C77C100020CB3B
S903FFFFFE

--- In 6..., "Edvard Karpicz" wrote:
>
> Default PPAGE is 0? That's good news for you, you don't need to do anything.
> Your FPGA should be accessible at 0x8000 out of reset in normal expanded
> mode.
>
> You said you don't need a lot of flash. So 32kB of nonbanked flash
> (0x4000..0x7FFF and 0xC000..0xFFFF) should suffice, right? So no need to
> write to PPAGE register.
>
> Edward
>
> ----- Original Message -----
> From: "imtiyazfmn"
> To: <6...>
> Sent: Tuesday, September 13, 2011 4:38 PM
> Subject: [68HC12] Re: 9s12d64 -External memory access
> > Can you please suggest me that how can i change PPAGE in my code memory
> > for access external memory?
> > And also please suggest that how to set PPAGE for 1st time when my device
> > is power on/Reset because its default PPAGE VALUE is zero at reset and my
> > fixed flash is on 3F PPAGE value ? will it automatically set at reset
> > vector location or what?
> >
> > Imtiyaz
> >
> >
> > --- In 6..., "Edvard Karpicz" wrote:
> >>
> >> Single external device with few addresses? It doesn't make sense to use
> >> external bus on S12D. Bitbanging you could use less pins for the same
> >> task.
> >>
> >> Since you are going to feed external clock to S12D, don't omit that Vhi
> >> of
> >> this signal should be not higher than Vddpll (~2.5V).
> >>
> >> You don't need to disable flash on 0x8000, you just need to set PPAGE
> >> register to any value from 0 to 0x3B. In expanded mode pages 0x3C-0x3F
> >> will
> >> map internal D64 flash to 0x8000, pages 0-0x3B - external memory.
> >>
> >> Edward
> >>
> >>
> >> ----- Original Message -----
> >> From: "imtiyazfmn"
> >> To: <6...>
> >> Sent: Friday, September 09, 2011 4:44 PM
> >> Subject: [68HC12] Re: 9s12d64 -External memory access
> >>
> >>
> >> > Thanks for reply..
> >> > Actually we will use only FPGA on external bus and my program size is
> >> > also
> >> > less then 5k and we don't want to change in firmware (like bitbang )
> >> > because decoding logic is insight of FPGA and we will 10MHZ external
> >> > clock
> >> > feed to micro with disable internal PLL .
> >> > So please suggest me how can i disable flash on ox8000 to 0xBFFF adress
> >> > location?
> >> > If any other thing that i need to confirm please suggest?
> >> >
> >> > --- In 6..., "Edvardas" wrote:
> >> >>
> >> >> S12D multiplexed external memory interface is not as easy to use as it
> >> >> was
> >> >> on HC11. What else do you plan to interface with ext.memory bus? If
> >> >> none,
> >> >> then just bitbang those data, address and CS lines. S12D bus clock is
> >> >> >6
> >> >> times faster than HC11 with 16MHz crystal. If indeed you need to
> >> >> access a
> >> >> lot of address space, then better choose S12XD, S12XA or S12XE MCU's.
> >> >> Of
> >> >> course you may dislike the need to choose only >4 pins packages.
> >> >> But
> >> >> interfacing to S12X memory bus is easy, both codewise and HW-wise.
> >> >>
> >> >> 0x8000 address can be used, but then you will be either limited to
> >> >> 32kB
> >> >> of
> >> >> nonbanked program memory, or not access your FPGA from banked
> >> >> routines.
> >> >>
> >> >> Can't help you with Cosmic.
> >> >>
> >> >> Edward
> >> >>
> >> >> ----- Original Message -----
> >> >> From: "imtiyazfmn"
> >> >> To: <6...>
> >> >> Sent: Thursday, September 08, 2011 10:38 PM
> >> >> Subject: [68HC12] 9s12d64 -External memory access
> >> >>
> >> >>
> >> >> > Hello,
> >> >> > I am going t use 9s12d64 for my older design with replacing this.In
> >> >> > older
> >> >> > design MC68HC11 was used.on that design an FPGA used on 0x8000 to
> >> >> > 0x803f
> >> >> > adress.So now i wanted to use same adress for an FPGA so is it
> >> >> > possible
> >> >> > in
> >> >> > 9s12d64 controller?
> >> >> > Since i have read that 0x8000 to 0xBFFF is used for program memory
> >> >> > using
> >> >> > page window.And insight of micro internal flash is available in this
> >> >> > location so i am thinking that i can not used for external FPGA
> >> >> > access.
> >> >> > So please anyone can suggest that can i used that location for
> >> >> > external
> >> >> > FPGA access for read and write? if yes please give me setting of
> >> >> > internal
> >> >> > registor to disble internal flash on that location ?
> >> >> > Also please suggest linker file section to difine it external Read
> >> >> > write
> >> >> > memory in cosmic compiler linker file (lkf file).
> >> >> >
> >> >> >
> >> >> >
> >> >> >
> >> >> >
> >> >> >
Is this code running? Do you run it using some BDM debugger? I'm asking
because reset vector in you S-records is not specified.
I see no other reasons why it may refuse to switch expanded mode.

Edward

----- Original Message -----
From: "imtiyazfmn"
To: <6...>
Sent: Friday, September 30, 2011 8:42 PM
Subject: [68HC12] Re: 9s12d64 -External memory access
> Hello,
> Please help me in this regards..
> Now i have started testing of my new design.the problem is when i switched
> my micro in Expanded wide mode from single chip mode ,there are nothing
> exwctutuin inside.Eclk is at 5mhz on 10mhz crystal.but i have set ECLK as
> a external access not free running.And i am accessing external adress
> contineus in loop but nothing can seen on adress line also i can not see
> r/w pulse as low...for your ref code is as follow with s19 file.
>
> void main(void)
> {
> /* asserted when energize asserted (sys mon) */
>
> /*
> Protect the configuration register but allow changes to
> rest of EEPROM. This must be done in the first 64 clock
> cycles after reset.
> */
> /*BlockProtectReg = PTCON;*/
>
> /*
> Enable the internal oscillator to generate the programming
> voltage for the EEPROM. This is required because the 'E'
> frequency is less than 2 Mhz.
> */
> /*OptionReg = CSEL;*/
> MODE=0xE0; /* EXPANDED WIDE MODE*//* 0xC0 FOR NARROW EXA.*/
> INTCR=0x00;/*External IRQ Disable */
> PLLCTL=0xB1; /*PLL off */
> INITRM=0x10; /* remap RAM to 0x1000 */
> INITEE=0x09; /*remap EEPROM to 0x800 and initialize*/
> PEAR=0x04; /* R/W Enable on pin out of micro */
> EBICTL; /*eclk as a external */
> MISC=0x07; /* ECLK is stretched to one cycle,onchip flash/rom enable and
> 0x4000 to 0x7fff is used as external memory not flash memory */
> for(i=0;i<512;i++) /* delay */
> flag=0;
> Repeat:
> for(i=0;i<2;i++)
> {
> if(flag==0)
> StatToSlink=0x2aaa;
> else
> RdWrTest=0x5555;
>
> }
> if(flag==0)
> flag=1;
> else
> flag=0;
> goto Repeat;
> }
>
> S19 FILE
>
> S03B0000433A5C496D746979617A5C436F6E742E456E675C5265736F6C7665725C5331325C746573745F636F64655C546573745F533132442E483132C8
> S123FF8000000000000000000000000000000000000000000000000000000000000000005D
> S115FFA0000000000000C0090000000000000000C000C2
> S123C00087CF1FFF16C00D20FEC75B1E0BC6E05B0BC75B1EC6B15B3AC6105B10C6095B1287
> S123C020C6045B0AC6015B0EC6075B1387C77C100287C77C1000FD1002027D10028D02007D
> S123C0402DEF87C77C1002FC10002608CC2AAA7C80002006CC55557C8006FD1002027D10D2
> S11AC060028D00022DE1FC10002605CC0001200287C77C100020CB3B
> S903FFFFFE
> --- In 6..., "Edvard Karpicz" wrote:
>>
>> Default PPAGE is 0? That's good news for you, you don't need to do
>> anything.
>> Your FPGA should be accessible at 0x8000 out of reset in normal expanded
>> mode.
>>
>> You said you don't need a lot of flash. So 32kB of nonbanked flash
>> (0x4000..0x7FFF and 0xC000..0xFFFF) should suffice, right? So no need to
>> write to PPAGE register.
>>
>> Edward
>>
>> ----- Original Message -----
>> From: "imtiyazfmn"
>> To: <6...>
>> Sent: Tuesday, September 13, 2011 4:38 PM
>> Subject: [68HC12] Re: 9s12d64 -External memory access
>> > Can you please suggest me that how can i change PPAGE in my code memory
>> > for access external memory?
>> > And also please suggest that how to set PPAGE for 1st time when my
>> > device
>> > is power on/Reset because its default PPAGE VALUE is zero at reset and
>> > my
>> > fixed flash is on 3F PPAGE value ? will it automatically set at reset
>> > vector location or what?
>> >
>> > Imtiyaz
>> >
>> >
>> > --- In 6..., "Edvard Karpicz" wrote:
>> >>
>> >> Single external device with few addresses? It doesn't make sense to
>> >> use
>> >> external bus on S12D. Bitbanging you could use less pins for the same
>> >> task.
>> >>
>> >> Since you are going to feed external clock to S12D, don't omit that
>> >> Vhi
>> >> of
>> >> this signal should be not higher than Vddpll (~2.5V).
>> >>
>> >> You don't need to disable flash on 0x8000, you just need to set PPAGE
>> >> register to any value from 0 to 0x3B. In expanded mode pages 0x3C-0x3F
>> >> will
>> >> map internal D64 flash to 0x8000, pages 0-0x3B - external memory.
>> >>
>> >> Edward
>> >>
>> >>
>> >> ----- Original Message -----
>> >> From: "imtiyazfmn"
>> >> To: <6...>
>> >> Sent: Friday, September 09, 2011 4:44 PM
>> >> Subject: [68HC12] Re: 9s12d64 -External memory access
>> >>
>> >>
>> >> > Thanks for reply..
>> >> > Actually we will use only FPGA on external bus and my program size
>> >> > is
>> >> > also
>> >> > less then 5k and we don't want to change in firmware (like bitbang )
>> >> > because decoding logic is insight of FPGA and we will 10MHZ external
>> >> > clock
>> >> > feed to micro with disable internal PLL .
>> >> > So please suggest me how can i disable flash on ox8000 to 0xBFFF
>> >> > adress
>> >> > location?
>> >> > If any other thing that i need to confirm please suggest?
>> >> >
>> >> > --- In 6..., "Edvardas" wrote:
>> >> >>
>> >> >> S12D multiplexed external memory interface is not as easy to use as
>> >> >> it
>> >> >> was
>> >> >> on HC11. What else do you plan to interface with ext.memory bus? If
>> >> >> none,
>> >> >> then just bitbang those data, address and CS lines. S12D bus clock
>> >> >> is
>> >> >> >6
>> >> >> times faster than HC11 with 16MHz crystal. If indeed you need to
>> >> >> access a
>> >> >> lot of address space, then better choose S12XD, S12XA or S12XE
>> >> >> MCU's.
>> >> >> Of
>> >> >> course you may dislike the need to choose only >4 pins packages.
>> >> >> But
>> >> >> interfacing to S12X memory bus is easy, both codewise and HW-wise.
>> >> >>
>> >> >> 0x8000 address can be used, but then you will be either limited to
>> >> >> 32kB
>> >> >> of
>> >> >> nonbanked program memory, or not access your FPGA from banked
>> >> >> routines.
>> >> >>
>> >> >> Can't help you with Cosmic.
>> >> >>
>> >> >> Edward
>> >> >>
>> >> >> ----- Original Message -----
>> >> >> From: "imtiyazfmn"
>> >> >> To: <6...>
>> >> >> Sent: Thursday, September 08, 2011 10:38 PM
>> >> >> Subject: [68HC12] 9s12d64 -External memory access
>> >> >>
>> >> >>
>> >> >> > Hello,
>> >> >> > I am going t use 9s12d64 for my older design with replacing
>> >> >> > this.In
>> >> >> > older
>> >> >> > design MC68HC11 was used.on that design an FPGA used on 0x8000 to
>> >> >> > 0x803f
>> >> >> > adress.So now i wanted to use same adress for an FPGA so is it
>> >> >> > possible
>> >> >> > in
>> >> >> > 9s12d64 controller?
>> >> >> > Since i have read that 0x8000 to 0xBFFF is used for program
>> >> >> > memory
>> >> >> > using
>> >> >> > page window.And insight of micro internal flash is available in
>> >> >> > this
>> >> >> > location so i am thinking that i can not used for external FPGA
>> >> >> > access.
>> >> >> > So please anyone can suggest that can i used that location for
>> >> >> > external
>> >> >> > FPGA access for read and write? if yes please give me setting of
>> >> >> > internal
>> >> >> > registor to disble internal flash on that location ?
>> >> >> > Also please suggest linker file section to difine it external
>> >> >> > Read
>> >> >> > write
>> >> >> > memory in cosmic compiler linker file (lkf file).
>> >> >> >
>> >> >> >
>> >> >> >
>> >> >> >
>> >> >> >
>> >> >> >
Yes its run with using BDM debugger and at that time i can see external
signal also which is matched with ny code but while i am run it alone mean
without debugger,its not executing.

Imtiyaz
On Sat, Oct 1, 2011 at 1:00 PM, Edward Karpicz wrote:

> **
> Is this code running? Do you run it using some BDM debugger? I'm asking
> because reset vector in you S-records is not specified.
> I see no other reasons why it may refuse to switch expanded mode.
> Edward
>
> ----- Original Message -----
> From: "imtiyazfmn"
> To: <6...>
> Sent: Friday, September 30, 2011 8:42 PM
> Subject: [68HC12] Re: 9s12d64 -External memory access
>
> > Hello,
> > Please help me in this regards..
> > Now i have started testing of my new design.the problem is when i
> switched
> > my micro in Expanded wide mode from single chip mode ,there are nothing
> > exwctutuin inside.Eclk is at 5mhz on 10mhz crystal.but i have set ECLK as
>
> > a external access not free running.And i am accessing external adress
> > contineus in loop but nothing can seen on adress line also i can not see
> > r/w pulse as low...for your ref code is as follow with s19 file.
> >
> > void main(void)
> > {
> > /* asserted when energize asserted (sys mon) */
> >
> > /*
> > Protect the configuration register but allow changes to
> > rest of EEPROM. This must be done in the first 64 clock
> > cycles after reset.
> > */
> > /*BlockProtectReg = PTCON;*/
> >
> >
> >
> > /*
> > Enable the internal oscillator to generate the programming
> > voltage for the EEPROM. This is required because the 'E'
> > frequency is less than 2 Mhz.
> > */
> > /*OptionReg = CSEL;*/
> > MODE=0xE0; /* EXPANDED WIDE MODE*//* 0xC0 FOR NARROW EXA.*/
> > INTCR=0x00;/*External IRQ Disable */
> > PLLCTL=0xB1; /*PLL off */
> > INITRM=0x10; /* remap RAM to 0x1000 */
> > INITEE=0x09; /*remap EEPROM to 0x800 and initialize*/
> > PEAR=0x04; /* R/W Enable on pin out of micro */
> > EBICTL; /*eclk as a external */
> > MISC=0x07; /* ECLK is stretched to one cycle,onchip flash/rom enable and
> > 0x4000 to 0x7fff is used as external memory not flash memory */
> >
> >
> > for(i=0;i<512;i++) /* delay */
> > flag=0;
> > Repeat:
> > for(i=0;i<2;i++)
> > {
> > if(flag==0)
> > StatToSlink=0x2aaa;
> > else
> > RdWrTest=0x5555;
> >
> > }
> > if(flag==0)
> > flag=1;
> > else
> > flag=0;
> > goto Repeat;
> > }
> >
> > S19 FILE
> >
> >
> S03B0000433A5C496D746979617A5C436F6E742E456E675C5265736F6C7665725C5331325C746573745F636F64655C546573745F533132442E483132C8
> >
> S123FF8000000000000000000000000000000000000000000000000000000000000000005D
> > S115FFA0000000000000C0090000000000000000C000C2
> >
> S123C00087CF1FFF16C00D20FEC75B1E0BC6E05B0BC75B1EC6B15B3AC6105B10C6095B1287
> >
> S123C020C6045B0AC6015B0EC6075B1387C77C100287C77C1000FD1002027D10028D02007D
> >
> S123C0402DEF87C77C1002FC10002608CC2AAA7C80002006CC55557C8006FD1002027D10D2
> > S11AC060028D00022DE1FC10002605CC0001200287C77C100020CB3B
> > S903FFFFFE
> >
> >
> > --- In 6..., "Edvard Karpicz" wrote:
> >>
> >> Default PPAGE is 0? That's good news for you, you don't need to do
> >> anything.
> >> Your FPGA should be accessible at 0x8000 out of reset in normal expanded
> >> mode.
> >>
> >> You said you don't need a lot of flash. So 32kB of nonbanked flash
> >> (0x4000..0x7FFF and 0xC000..0xFFFF) should suffice, right? So no need to
> >> write to PPAGE register.
> >>
> >> Edward
> >>
> >> ----- Original Message -----
> >> From: "imtiyazfmn"
> >> To: <6...>
> >> Sent: Tuesday, September 13, 2011 4:38 PM
> >> Subject: [68HC12] Re: 9s12d64 -External memory access
> >>
> >>
> >> > Can you please suggest me that how can i change PPAGE in my code
> memory
> >> > for access external memory?
> >> > And also please suggest that how to set PPAGE for 1st time when my
> >> > device
> >> > is power on/Reset because its default PPAGE VALUE is zero at reset and
>
> >> > my
> >> > fixed flash is on 3F PPAGE value ? will it automatically set at reset
> >> > vector location or what?
> >> >
> >> > Imtiyaz
> >> >
> >> >
> >> > --- In 6..., "Edvard Karpicz" wrote:
> >> >>
> >> >> Single external device with few addresses? It doesn't make sense to
> >> >> use
> >> >> external bus on S12D. Bitbanging you could use less pins for the same
> >> >> task.
> >> >>
> >> >> Since you are going to feed external clock to S12D, don't omit that
> >> >> Vhi
> >> >> of
> >> >> this signal should be not higher than Vddpll (~2.5V).
> >> >>
> >> >> You don't need to disable flash on 0x8000, you just need to set PPAGE
> >> >> register to any value from 0 to 0x3B. In expanded mode pages
> 0x3C-0x3F
> >> >> will
> >> >> map internal D64 flash to 0x8000, pages 0-0x3B - external memory.
> >> >>
> >> >> Edward
> >> >>
> >> >>
> >> >> ----- Original Message -----
> >> >> From: "imtiyazfmn"
> >> >> To: <6...>
> >> >> Sent: Friday, September 09, 2011 4:44 PM
> >> >> Subject: [68HC12] Re: 9s12d64 -External memory access
> >> >>
> >> >>
> >> >> > Thanks for reply..
> >> >> > Actually we will use only FPGA on external bus and my program size
> >> >> > is
> >> >> > also
> >> >> > less then 5k and we don't want to change in firmware (like bitbang
> )
> >> >> > because decoding logic is insight of FPGA and we will 10MHZ
> external
> >> >> > clock
> >> >> > feed to micro with disable internal PLL .
> >> >> > So please suggest me how can i disable flash on ox8000 to 0xBFFF
> >> >> > adress
> >> >> > location?
> >> >> > If any other thing that i need to confirm please suggest?
> >> >> >
> >> >> > --- In 6..., "Edvardas" wrote:
> >> >> >>
> >> >> >> S12D multiplexed external memory interface is not as easy to use
> as
> >> >> >> it
> >> >> >> was
> >> >> >> on HC11. What else do you plan to interface with ext.memory bus?
> If
> >> >> >> none,
> >> >> >> then just bitbang those data, address and CS lines. S12D bus clock
>
> >> >> >> is
> >> >> >> >6
> >> >> >> times faster than HC11 with 16MHz crystal. If indeed you need to
> >> >> >> access a
> >> >> >> lot of address space, then better choose S12XD, S12XA or S12XE
> >> >> >> MCU's.
> >> >> >> Of
> >> >> >> course you may dislike the need to choose only >4 pins
> packages.
> >> >> >> But
> >> >> >> interfacing to S12X memory bus is easy, both codewise and HW-wise.
> >> >> >>
> >> >> >> 0x8000 address can be used, but then you will be either limited to
> >> >> >> 32kB
> >> >> >> of
> >> >> >> nonbanked program memory, or not access your FPGA from banked
> >> >> >> routines.
> >> >> >>
> >> >> >> Can't help you with Cosmic.
> >> >> >>
> >> >> >> Edward
> >> >> >>
> >> >> >> ----- Original Message -----
> >> >> >> From: "imtiyazfmn"
> >> >> >> To: <6...>
> >> >> >> Sent: Thursday, September 08, 2011 10:38 PM
> >> >> >> Subject: [68HC12] 9s12d64 -External memory access
> >> >> >>
> >> >> >>
> >> >> >> > Hello,
> >> >> >> > I am going t use 9s12d64 for my older design with replacing
> >> >> >> > this.In
> >> >> >> > older
> >> >> >> > design MC68HC11 was used.on that design an FPGA used on 0x8000
> to
> >> >> >> > 0x803f
> >> >> >> > adress.So now i wanted to use same adress for an FPGA so is it
> >> >> >> > possible
> >> >> >> > in
> >> >> >> > 9s12d64 controller?
> >> >> >> > Since i have read that 0x8000 to 0xBFFF is used for program
> >> >> >> > memory
> >> >> >> > using
> >> >> >> > page window.And insight of micro internal flash is available in
> >> >> >> > this
> >> >> >> > location so i am thinking that i can not used for external FPGA
> >> >> >> > access.
> >> >> >> > So please anyone can suggest that can i used that location for
> >> >> >> > external
> >> >> >> > FPGA access for read and write? if yes please give me setting of
> >> >> >> > internal
> >> >> >> > registor to disble internal flash on that location ?
> >> >> >> > Also please suggest linker file section to difine it external
> >> >> >> > Read
> >> >> >> > write
> >> >> >> > memory in cosmic compiler linker file (lkf file).
> >> >> >> >
> >> >> >> >
> >> >> >> >
> >> >> >> >
> >> >> >> >
> >> >> >> >
Like I said, something wrong is with reset vector. It is not defined in your
S records.

Edward

----- Original Message -----
From: "imtiyaz memon"
To: <6...>
Sent: Saturday, October 01, 2011 9:02 PM
Subject: Re: [68HC12] Re: 9s12d64 -External memory access
> Yes its run with using BDM debugger and at that time i can see external
> signal also which is matched with ny code but while i am run it alone mean
> without debugger,its not executing.
>
> Imtiyaz
> On Sat, Oct 1, 2011 at 1:00 PM, Edward Karpicz wrote:
>
>> **
>> Is this code running? Do you run it using some BDM debugger? I'm asking
>> because reset vector in you S-records is not specified.
>> I see no other reasons why it may refuse to switch expanded mode.
>> Edward
>>
>> ----- Original Message -----
>> From: "imtiyazfmn"
>> To: <6...>
>> Sent: Friday, September 30, 2011 8:42 PM
>> Subject: [68HC12] Re: 9s12d64 -External memory access
>>
>> > Hello,
>> > Please help me in this regards..
>> > Now i have started testing of my new design.the problem is when i
>> switched
>> > my micro in Expanded wide mode from single chip mode ,there are nothing
>> > exwctutuin inside.Eclk is at 5mhz on 10mhz crystal.but i have set ECLK
>> > as
>>
>> > a external access not free running.And i am accessing external adress
>> > contineus in loop but nothing can seen on adress line also i can not
>> > see
>> > r/w pulse as low...for your ref code is as follow with s19 file.
>> >
>> > void main(void)
>> > {
>> > /* asserted when energize asserted (sys mon) */
>> >
>> > /*
>> > Protect the configuration register but allow changes to
>> > rest of EEPROM. This must be done in the first 64 clock
>> > cycles after reset.
>> > */
>> > /*BlockProtectReg = PTCON;*/
>> >
>> >
>> >
>> > /*
>> > Enable the internal oscillator to generate the programming
>> > voltage for the EEPROM. This is required because the 'E'
>> > frequency is less than 2 Mhz.
>> > */
>> > /*OptionReg = CSEL;*/
>> > MODE=0xE0; /* EXPANDED WIDE MODE*//* 0xC0 FOR NARROW EXA.*/
>> > INTCR=0x00;/*External IRQ Disable */
>> > PLLCTL=0xB1; /*PLL off */
>> > INITRM=0x10; /* remap RAM to 0x1000 */
>> > INITEE=0x09; /*remap EEPROM to 0x800 and initialize*/
>> > PEAR=0x04; /* R/W Enable on pin out of micro */
>> > EBICTL; /*eclk as a external */
>> > MISC=0x07; /* ECLK is stretched to one cycle,onchip flash/rom enable
>> > and
>> > 0x4000 to 0x7fff is used as external memory not flash memory */
>> >
>> >
>> > for(i=0;i<512;i++) /* delay */
>> > flag=0;
>> > Repeat:
>> > for(i=0;i<2;i++)
>> > {
>> > if(flag==0)
>> > StatToSlink=0x2aaa;
>> > else
>> > RdWrTest=0x5555;
>> >
>> > }
>> > if(flag==0)
>> > flag=1;
>> > else
>> > flag=0;
>> > goto Repeat;
>> > }
>> >
>> > S19 FILE
>> >
>> >
>> S03B0000433A5C496D746979617A5C436F6E742E456E675C5265736F6C7665725C5331325C746573745F636F64655C546573745F533132442E483132C8
>> >
>> S123FF8000000000000000000000000000000000000000000000000000000000000000005D
>> > S115FFA0000000000000C0090000000000000000C000C2
>> >
>> S123C00087CF1FFF16C00D20FEC75B1E0BC6E05B0BC75B1EC6B15B3AC6105B10C6095B1287
>> >
>> S123C020C6045B0AC6015B0EC6075B1387C77C100287C77C1000FD1002027D10028D02007D
>> >
>> S123C0402DEF87C77C1002FC10002608CC2AAA7C80002006CC55557C8006FD1002027D10D2
>> > S11AC060028D00022DE1FC10002605CC0001200287C77C100020CB3B
>> > S903FFFFFE
>> >
>> >
>> > --- In 6..., "Edvard Karpicz" wrote:
>> >>
>> >> Default PPAGE is 0? That's good news for you, you don't need to do
>> >> anything.
>> >> Your FPGA should be accessible at 0x8000 out of reset in normal
>> >> expanded
>> >> mode.
>> >>
>> >> You said you don't need a lot of flash. So 32kB of nonbanked flash
>> >> (0x4000..0x7FFF and 0xC000..0xFFFF) should suffice, right? So no need
>> >> to
>> >> write to PPAGE register.
>> >>
>> >> Edward
>> >>
>> >> ----- Original Message -----
>> >> From: "imtiyazfmn"
>> >> To: <6...>
>> >> Sent: Tuesday, September 13, 2011 4:38 PM
>> >> Subject: [68HC12] Re: 9s12d64 -External memory access
>> >>
>> >>
>> >> > Can you please suggest me that how can i change PPAGE in my code
>> memory
>> >> > for access external memory?
>> >> > And also please suggest that how to set PPAGE for 1st time when my
>> >> > device
>> >> > is power on/Reset because its default PPAGE VALUE is zero at reset
>> >> > and
>>
>> >> > my
>> >> > fixed flash is on 3F PPAGE value ? will it automatically set at
>> >> > reset
>> >> > vector location or what?
>> >> >
>> >> > Imtiyaz
>> >> >
>> >> >
>> >> > --- In 6..., "Edvard Karpicz" wrote:
>> >> >>
>> >> >> Single external device with few addresses? It doesn't make sense to
>> >> >> use
>> >> >> external bus on S12D. Bitbanging you could use less pins for the
>> >> >> same
>> >> >> task.
>> >> >>
>> >> >> Since you are going to feed external clock to S12D, don't omit that
>> >> >> Vhi
>> >> >> of
>> >> >> this signal should be not higher than Vddpll (~2.5V).
>> >> >>
>> >> >> You don't need to disable flash on 0x8000, you just need to set
>> >> >> PPAGE
>> >> >> register to any value from 0 to 0x3B. In expanded mode pages
>> 0x3C-0x3F
>> >> >> will
>> >> >> map internal D64 flash to 0x8000, pages 0-0x3B - external memory.
>> >> >>
>> >> >> Edward
>> >> >>
>> >> >>
>> >> >> ----- Original Message -----
>> >> >> From: "imtiyazfmn"
>> >> >> To: <6...>
>> >> >> Sent: Friday, September 09, 2011 4:44 PM
>> >> >> Subject: [68HC12] Re: 9s12d64 -External memory access
>> >> >>
>> >> >>
>> >> >> > Thanks for reply..
>> >> >> > Actually we will use only FPGA on external bus and my program
>> >> >> > size
>> >> >> > is
>> >> >> > also
>> >> >> > less then 5k and we don't want to change in firmware (like
>> >> >> > bitbang
>> )
>> >> >> > because decoding logic is insight of FPGA and we will 10MHZ
>> external
>> >> >> > clock
>> >> >> > feed to micro with disable internal PLL .
>> >> >> > So please suggest me how can i disable flash on ox8000 to 0xBFFF
>> >> >> > adress
>> >> >> > location?
>> >> >> > If any other thing that i need to confirm please suggest?
>> >> >> >
>> >> >> > --- In 6..., "Edvardas" wrote:
>> >> >> >>
>> >> >> >> S12D multiplexed external memory interface is not as easy to use
>> as
>> >> >> >> it
>> >> >> >> was
>> >> >> >> on HC11. What else do you plan to interface with ext.memory bus?
>> If
>> >> >> >> none,
>> >> >> >> then just bitbang those data, address and CS lines. S12D bus
>> >> >> >> clock
>>
>> >> >> >> is
>> >> >> >> >6
>> >> >> >> times faster than HC11 with 16MHz crystal. If indeed you need to
>> >> >> >> access a
>> >> >> >> lot of address space, then better choose S12XD, S12XA or S12XE
>> >> >> >> MCU's.
>> >> >> >> Of
>> >> >> >> course you may dislike the need to choose only >4 pins
>> packages.
>> >> >> >> But
>> >> >> >> interfacing to S12X memory bus is easy, both codewise and
>> >> >> >> HW-wise.
>> >> >> >>
>> >> >> >> 0x8000 address can be used, but then you will be either limited
>> >> >> >> to
>> >> >> >> 32kB
>> >> >> >> of
>> >> >> >> nonbanked program memory, or not access your FPGA from banked
>> >> >> >> routines.
>> >> >> >>
>> >> >> >> Can't help you with Cosmic.
>> >> >> >>
>> >> >> >> Edward
>> >> >> >>
>> >> >> >> ----- Original Message -----
>> >> >> >> From: "imtiyazfmn"
>> >> >> >> To: <6...>
>> >> >> >> Sent: Thursday, September 08, 2011 10:38 PM
>> >> >> >> Subject: [68HC12] 9s12d64 -External memory access
>> >> >> >>
>> >> >> >>
>> >> >> >> > Hello,
>> >> >> >> > I am going t use 9s12d64 for my older design with replacing
>> >> >> >> > this.In
>> >> >> >> > older
>> >> >> >> > design MC68HC11 was used.on that design an FPGA used on 0x8000
>> to
>> >> >> >> > 0x803f
>> >> >> >> > adress.So now i wanted to use same adress for an FPGA so is it
>> >> >> >> > possible
>> >> >> >> > in
>> >> >> >> > 9s12d64 controller?
>> >> >> >> > Since i have read that 0x8000 to 0xBFFF is used for program
>> >> >> >> > memory
>> >> >> >> > using
>> >> >> >> > page window.And insight of micro internal flash is available
>> >> >> >> > in
>> >> >> >> > this
>> >> >> >> > location so i am thinking that i can not used for external
>> >> >> >> > FPGA
>> >> >> >> > access.
>> >> >> >> > So please anyone can suggest that can i used that location for
>> >> >> >> > external
>> >> >> >> > FPGA access for read and write? if yes please give me setting
>> >> >> >> > of
>> >> >> >> > internal
>> >> >> >> > registor to disble internal flash on that location ?
>> >> >> >> > Also please suggest linker file section to difine it external
>> >> >> >> > Read
>> >> >> >> > write
>> >> >> >> > memory in cosmic compiler linker file (lkf file).
>> >> >> >> >
>> >> >> >> >
>> >> >> >> >
>> >> >> >> >
>> >> >> >> >
>> >> >> >> >