9s12d64 -Trouble with PLL and filter

Started by imtiyazfmn November 1, 2011
Hello,
I am using 5 mhz CLK in source and i need 1.25 mhz Bus clk so i used internal PLL for that ,i have done following thing for that is
1)SYNR;
2)REFDIV;
EX CODE IS:
/*PLLCTL=0xB1; /*PLL off */
/*goto PLL_BYPASS; */
CLKSEL=0x00;
REFDV; /* BUSCLK=5MHZ*(0+1)/(3+1) */
SYNR;
Lock_loop:
for (i=0; i< 30000;i++){} /* Delay some time ... */
bit=CRGFLG & LOCK;
if(bit ==0x00)
goto Lock_loop;

CLKSEL=0x80; /* CLK=PLLCLK */
CRGFLG=0x10; /* LOCKIF Cleared */

3) above code is tested for input clk = 10mhz and bus clk is comming = 2.5 mhz
4)for this filter compnent on XFC are as follow
Rc7 OHM
cs= 81 nf
cp=8.1 nf
so i put rc4 ohm..cs0nf...cp= 10 nf

After this the Bus clock is not comming so kindly give your suggestion if any thing i had miissed out.
For your information with 10mhz clk source ,2.5 mhz was comming at that time RS = 622 CS 100 NF AND CP NF

Imtiyaz

Hi. Your problem may be similar to the one I was having earlier this year. There are several sides to it. You should refer to my earlier postings for more detail on the code I used.

There is a mask error in some HC12's that sets bits upon writing to SYNR and REFDIV so it looks as if the PLL is locked when it is not.

Also depending on the locked oscillator phase and speed of locking, LOCK may never turn on even though the system is locked. So you need to look at the TRACK bit for a while and it turns out that is the more reliable indicator. If a valid LOCK is seen you will be locked ... but absence of a LOCK signal is not a sufficient indication of being unlocked.

The other, and more basic one, is that the LOCK/TRACK bits take a lot of time to see reality; I wait for at least a few hundred clock cycles before trusting their values. This is because they are only updated after a division time that uses more than 100 clock cycles to occur. So you can easily convince yourself that you have seen 10 valid LOCK indications, and so think that you are locked, whereas you are only looking at the same bad data bit 10 times.

In conclusion; set the SYNR and REFDIV, then tell the PLL to turn on, then wait for a few hundred clock cycles, then check LOCK and TRACK with delays of a couple of hundred cycles in between each check. If you find that either bit has been set for say 10 views, you will know that you are locked correctly.

Chris H.

--- In 6..., "imtiyazfmn" wrote:
>
> Hello,
> I am using 5 mhz CLK in source and i need 1.25 mhz Bus clk so i used internal PLL for that ,i have done following thing for that is
> 1)SYNR;
> 2)REFDIV;
> EX CODE IS:
> /*PLLCTL=0xB1; /*PLL off */
> /*goto PLL_BYPASS; */
> CLKSEL=0x00;
> REFDV; /* BUSCLK=5MHZ*(0+1)/(3+1) */
> SYNR;
> Lock_loop:
> for (i=0; i< 30000;i++){} /* Delay some time ... */
> bit=CRGFLG & LOCK;
> if(bit ==0x00)
> goto Lock_loop;
>
> CLKSEL=0x80; /* CLK=PLLCLK */
> CRGFLG=0x10; /* LOCKIF Cleared */
>
> 3) above code is tested for input clk = 10mhz and bus clk is comming = 2.5 mhz
> 4)for this filter compnent on XFC are as follow
> Rc7 OHM
> cs= 81 nf
> cp=8.1 nf
> so i put rc4 ohm..cs0nf...cp= 10 nf
>
> After this the Bus clock is not comming so kindly give your suggestion if any thing i had miissed out.
> For your information with 10mhz clk source ,2.5 mhz was comming at that time RS = 622 CS 100 NF AND CP NF
>
> Imtiyaz
>

Thanks for reply...
Still i am struggling for PLL I did same changes as you mentioned in your
earlier reply ,I have seen that MICRO is not coming in tracking mode
(track bit in CRGFLG is zero) ,all times it reads 00 even after multiple
of 128 cycles,kindly suggest for same.

Imtiyaz

On Wed, Nov 2, 2011 at 11:34 AM, Chris wrote:

> **
> Hi. Your problem may be similar to the one I was having earlier this year.
> There are several sides to it. You should refer to my earlier postings for
> more detail on the code I used.
>
> There is a mask error in some HC12's that sets bits upon writing to SYNR
> and REFDIV so it looks as if the PLL is locked when it is not.
>
> Also depending on the locked oscillator phase and speed of locking, LOCK
> may never turn on even though the system is locked. So you need to look at
> the TRACK bit for a while and it turns out that is the more reliable
> indicator. If a valid LOCK is seen you will be locked ... but absence of a
> LOCK signal is not a sufficient indication of being unlocked.
>
> The other, and more basic one, is that the LOCK/TRACK bits take a lot of
> time to see reality; I wait for at least a few hundred clock cycles before
> trusting their values. This is because they are only updated after a
> division time that uses more than 100 clock cycles to occur. So you can
> easily convince yourself that you have seen 10 valid LOCK indications, and
> so think that you are locked, whereas you are only looking at the same bad
> data bit 10 times.
>
> In conclusion; set the SYNR and REFDIV, then tell the PLL to turn on, then
> wait for a few hundred clock cycles, then check LOCK and TRACK with delays
> of a couple of hundred cycles in between each check. If you find that
> either bit has been set for say 10 views, you will know that you are locked
> correctly.
>
> Chris H.
> --- In 6..., "imtiyazfmn" wrote:
> >
> > Hello,
> > I am using 5 mhz CLK in source and i need 1.25 mhz Bus clk so i used
> internal PLL for that ,i have done following thing for that is
> > 1)SYNR;
> > 2)REFDIV;
> > EX CODE IS:
> > /*PLLCTL=0xB1; /*PLL off */
> > /*goto PLL_BYPASS; */
> > CLKSEL=0x00;
> > REFDV; /* BUSCLK=5MHZ*(0+1)/(3+1) */
> > SYNR;
> > Lock_loop:
> > for (i=0; i< 30000;i++){} /* Delay some time ... */
> > bit=CRGFLG & LOCK;
> > if(bit ==0x00)
> > goto Lock_loop;
> >
> > CLKSEL=0x80; /* CLK=PLLCLK */
> > CRGFLG=0x10; /* LOCKIF Cleared */
> >
> > 3) above code is tested for input clk = 10mhz and bus clk is comming > 2.5 mhz
> > 4)for this filter compnent on XFC are as follow
> > Rc7 OHM
> > cs= 81 nf
> > cp=8.1 nf
> > so i put rc4 ohm..cs0nf...cp= 10 nf
> >
> > After this the Bus clock is not comming so kindly give your suggestion
> if any thing i had miissed out.
> > For your information with 10mhz clk source ,2.5 mhz was comming at that
> time RS = 622 CS 100 NF AND CP NF
> >
> > Imtiyaz
> >
>


So your problem must be in some setup that is missing; please post the full code you are using to set up the clock and PLL so we can all see where the problem may be.

--- In 6..., imtiyaz memon wrote:
>
> Thanks for reply...
> Still i am struggling for PLL I did same changes as you mentioned in your
> earlier reply ,I have seen that MICRO is not coming in tracking mode
> (track bit in CRGFLG is zero) ,all times it reads 00 even after multiple
> of 128 cycles,kindly suggest for same.
>
> Imtiyaz
> On Wed, Nov 2, 2011 at 11:34 AM, Chris wrote:
>
> > **
> >
> >
> >
> >
> > Hi. Your problem may be similar to the one I was having earlier this year.
> > There are several sides to it. You should refer to my earlier postings for
> > more detail on the code I used.
> >
> > There is a mask error in some HC12's that sets bits upon writing to SYNR
> > and REFDIV so it looks as if the PLL is locked when it is not.
> >
> > Also depending on the locked oscillator phase and speed of locking, LOCK
> > may never turn on even though the system is locked. So you need to look at
> > the TRACK bit for a while and it turns out that is the more reliable
> > indicator. If a valid LOCK is seen you will be locked ... but absence of a
> > LOCK signal is not a sufficient indication of being unlocked.
> >
> > The other, and more basic one, is that the LOCK/TRACK bits take a lot of
> > time to see reality; I wait for at least a few hundred clock cycles before
> > trusting their values. This is because they are only updated after a
> > division time that uses more than 100 clock cycles to occur. So you can
> > easily convince yourself that you have seen 10 valid LOCK indications, and
> > so think that you are locked, whereas you are only looking at the same bad
> > data bit 10 times.
> >
> > In conclusion; set the SYNR and REFDIV, then tell the PLL to turn on, then
> > wait for a few hundred clock cycles, then check LOCK and TRACK with delays
> > of a couple of hundred cycles in between each check. If you find that
> > either bit has been set for say 10 views, you will know that you are locked
> > correctly.
> >
> > Chris H.
> >
> >
> > --- In 6..., "imtiyazfmn" wrote:
> > >
> > > Hello,
> > > I am using 5 mhz CLK in source and i need 1.25 mhz Bus clk so i used
> > internal PLL for that ,i have done following thing for that is
> > > 1)SYNR;
> > > 2)REFDIV;
> > > EX CODE IS:
> > > /*PLLCTL=0xB1; /*PLL off */
> > > /*goto PLL_BYPASS; */
> > > CLKSEL=0x00;
> > > REFDV; /* BUSCLK=5MHZ*(0+1)/(3+1) */
> > > SYNR;
> > > Lock_loop:
> > > for (i=0; i< 30000;i++){} /* Delay some time ... */
> > > bit=CRGFLG & LOCK;
> > > if(bit ==0x00)
> > > goto Lock_loop;
> > >
> > > CLKSEL=0x80; /* CLK=PLLCLK */
> > > CRGFLG=0x10; /* LOCKIF Cleared */
> > >
> > > 3) above code is tested for input clk = 10mhz and bus clk is comming > > 2.5 mhz
> > > 4)for this filter compnent on XFC are as follow
> > > Rc7 OHM
> > > cs= 81 nf
> > > cp=8.1 nf
> > > so i put rc4 ohm..cs0nf...cp= 10 nf
> > >
> > > After this the Bus clock is not comming so kindly give your suggestion
> > if any thing i had miissed out.
> > > For your information with 10mhz clk source ,2.5 mhz was comming at that
> > time RS = 622 CS 100 NF AND CP NF
> > >
> > > Imtiyaz
> > >
> >
> >
> >
>
>

I have posted here the full code which is using to set up the clock and PLL
Kindly analyzed and give youe feedback.
PLLCTL=0xB1; /*PLL off */
/*goto PLL_BYPASS; */
CLKSEL=0x00;
REFDV; /* BUSCLK=5MHZ*(0+1)/(3+1) */
SYNR;
CRGFLG=0xFF;
PLLCTL=0xF1;
for (i=0; i< 2200;i++){}
Lock_loop:
for (i=0; i< 22;i++){} /* Delay time for 127 clk cycle... */
if (((CRGFLG & TRACK)==0x04) && ((CRGFLG & LOCK)==0x08) )
{
ii=ii+1;
if(ii<9)
goto Lock_loop;
}
else
{
ii=0;
goto Lock_loop;
}

CLKSEL=0x80; /* CLK=PLLCLK */
CRGFLG=0x10; /* LOCKIF Cleared */
Imtiyaz

On Thu, Nov 3, 2011 at 12:11 PM, Chris wrote:

> **
> So your problem must be in some setup that is missing; please post the
> full code you are using to set up the clock and PLL so we can all see where
> the problem may be.
>
> --- In 6..., imtiyaz memon wrote:
> >
> > Thanks for reply...
> > Still i am struggling for PLL I did same changes as you mentioned in your
> > earlier reply ,I have seen that MICRO is not coming in tracking mode
> > (track bit in CRGFLG is zero) ,all times it reads 00 even after multiple
> > of 128 cycles,kindly suggest for same.
> >
> > Imtiyaz
> >
> >
> >
> >
> > On Wed, Nov 2, 2011 at 11:34 AM, Chris wrote:
> >
> > > **
>
> > >
> > >
> > >
> > >
> > > Hi. Your problem may be similar to the one I was having earlier this
> year.
> > > There are several sides to it. You should refer to my earlier postings
> for
> > > more detail on the code I used.
> > >
> > > There is a mask error in some HC12's that sets bits upon writing to
> SYNR
> > > and REFDIV so it looks as if the PLL is locked when it is not.
> > >
> > > Also depending on the locked oscillator phase and speed of locking,
> LOCK
> > > may never turn on even though the system is locked. So you need to
> look at
> > > the TRACK bit for a while and it turns out that is the more reliable
> > > indicator. If a valid LOCK is seen you will be locked ... but absence
> of a
> > > LOCK signal is not a sufficient indication of being unlocked.
> > >
> > > The other, and more basic one, is that the LOCK/TRACK bits take a lot
> of
> > > time to see reality; I wait for at least a few hundred clock cycles
> before
> > > trusting their values. This is because they are only updated after a
> > > division time that uses more than 100 clock cycles to occur. So you can
> > > easily convince yourself that you have seen 10 valid LOCK indications,
> and
> > > so think that you are locked, whereas you are only looking at the same
> bad
> > > data bit 10 times.
> > >
> > > In conclusion; set the SYNR and REFDIV, then tell the PLL to turn on,
> then
> > > wait for a few hundred clock cycles, then check LOCK and TRACK with
> delays
> > > of a couple of hundred cycles in between each check. If you find that
> > > either bit has been set for say 10 views, you will know that you are
> locked
> > > correctly.
> > >
> > > Chris H.
> > >
> > >
> > > --- In 6..., "imtiyazfmn" wrote:
> > > >
> > > > Hello,
> > > > I am using 5 mhz CLK in source and i need 1.25 mhz Bus clk so i used
> > > internal PLL for that ,i have done following thing for that is
> > > > 1)SYNR;
> > > > 2)REFDIV;
> > > > EX CODE IS:
> > > > /*PLLCTL=0xB1; /*PLL off */
> > > > /*goto PLL_BYPASS; */
> > > > CLKSEL=0x00;
> > > > REFDV; /* BUSCLK=5MHZ*(0+1)/(3+1) */
> > > > SYNR;
> > > > Lock_loop:
> > > > for (i=0; i< 30000;i++){} /* Delay some time ... */
> > > > bit=CRGFLG & LOCK;
> > > > if(bit ==0x00)
> > > > goto Lock_loop;
> > > >
> > > > CLKSEL=0x80; /* CLK=PLLCLK */
> > > > CRGFLG=0x10; /* LOCKIF Cleared */
> > > >
> > > > 3) above code is tested for input clk = 10mhz and bus clk is comming
> > > > 2.5 mhz
> > > > 4)for this filter compnent on XFC are as follow
> > > > Rc7 OHM
> > > > cs= 81 nf
> > > > cp=8.1 nf
> > > > so i put rc4 ohm..cs0nf...cp= 10 nf
> > > >
> > > > After this the Bus clock is not comming so kindly give your
> suggestion
> > > if any thing i had miissed out.
> > > > For your information with 10mhz clk source ,2.5 mhz was comming at
> that
> > > time RS = 622 CS 100 NF AND CP NF
> > > >
> > > > Imtiyaz
> > > >
> > >
> > >
> > >
> >
> >
> >
> >
>


Hello.
I found that FVCO locking range is from 8 MHz to 50mhz in data sheet
and i have calculated Fvco=2.5mhz which is wrong right?
so that might be reason of not working PLL but before that i ran PLL when
Fvco=5mhz!!!!!....

Now please suggest that what i have to do ,to get 1.25 mhz bus freq from 5
mhz external clk ?

Imtiyaz
On Thu, Nov 3, 2011 at 12:54 PM, imtiyaz memon wrote:

> I have posted here the full code which is using to set up the clock and
> PLL
> Kindly analyzed and give youe feedback.
> PLLCTL=0xB1; /*PLL off */
> /*goto PLL_BYPASS; */
> CLKSEL=0x00;
> REFDV; /* BUSCLK=5MHZ*(0+1)/(3+1) */
> SYNR;
> CRGFLG=0xFF;
> PLLCTL=0xF1;
> for (i=0; i< 2200;i++){}
> Lock_loop:
> for (i=0; i< 22;i++){} /* Delay time for 127 clk cycle... */
> if (((CRGFLG & TRACK)==0x04) && ((CRGFLG & LOCK)==0x08) )
> {
> ii=ii+1;
> if(ii<9)
> goto Lock_loop;
> }
> else
> {
> ii=0;
> goto Lock_loop;
> }
>
> CLKSEL=0x80; /* CLK=PLLCLK */
> CRGFLG=0x10; /* LOCKIF Cleared */
> Imtiyaz
>
> On Thu, Nov 3, 2011 at 12:11 PM, Chris wrote:
>
>> **
>> So your problem must be in some setup that is missing; please post the
>> full code you are using to set up the clock and PLL so we can all see where
>> the problem may be.
>>
>> --- In 6..., imtiyaz memon wrote:
>> >
>> > Thanks for reply...
>> > Still i am struggling for PLL I did same changes as you mentioned in
>> your
>> > earlier reply ,I have seen that MICRO is not coming in tracking mode
>> > (track bit in CRGFLG is zero) ,all times it reads 00 even after multiple
>> > of 128 cycles,kindly suggest for same.
>> >
>> > Imtiyaz
>> >
>> >
>> >
>> >
>> > On Wed, Nov 2, 2011 at 11:34 AM, Chris wrote:
>> >
>> > > **
>>
>> > >
>> > >
>> > >
>> > >
>> > > Hi. Your problem may be similar to the one I was having earlier this
>> year.
>> > > There are several sides to it. You should refer to my earlier
>> postings for
>> > > more detail on the code I used.
>> > >
>> > > There is a mask error in some HC12's that sets bits upon writing to
>> SYNR
>> > > and REFDIV so it looks as if the PLL is locked when it is not.
>> > >
>> > > Also depending on the locked oscillator phase and speed of locking,
>> LOCK
>> > > may never turn on even though the system is locked. So you need to
>> look at
>> > > the TRACK bit for a while and it turns out that is the more reliable
>> > > indicator. If a valid LOCK is seen you will be locked ... but absence
>> of a
>> > > LOCK signal is not a sufficient indication of being unlocked.
>> > >
>> > > The other, and more basic one, is that the LOCK/TRACK bits take a lot
>> of
>> > > time to see reality; I wait for at least a few hundred clock cycles
>> before
>> > > trusting their values. This is because they are only updated after a
>> > > division time that uses more than 100 clock cycles to occur. So you
>> can
>> > > easily convince yourself that you have seen 10 valid LOCK
>> indications, and
>> > > so think that you are locked, whereas you are only looking at the
>> same bad
>> > > data bit 10 times.
>> > >
>> > > In conclusion; set the SYNR and REFDIV, then tell the PLL to turn on,
>> then
>> > > wait for a few hundred clock cycles, then check LOCK and TRACK with
>> delays
>> > > of a couple of hundred cycles in between each check. If you find that
>> > > either bit has been set for say 10 views, you will know that you are
>> locked
>> > > correctly.
>> > >
>> > > Chris H.
>> > >
>> > >
>> > > --- In 6..., "imtiyazfmn" wrote:
>> > > >
>> > > > Hello,
>> > > > I am using 5 mhz CLK in source and i need 1.25 mhz Bus clk so i used
>> > > internal PLL for that ,i have done following thing for that is
>> > > > 1)SYNR;
>> > > > 2)REFDIV;
>> > > > EX CODE IS:
>> > > > /*PLLCTL=0xB1; /*PLL off */
>> > > > /*goto PLL_BYPASS; */
>> > > > CLKSEL=0x00;
>> > > > REFDV; /* BUSCLK=5MHZ*(0+1)/(3+1) */
>> > > > SYNR;
>> > > > Lock_loop:
>> > > > for (i=0; i< 30000;i++){} /* Delay some time ... */
>> > > > bit=CRGFLG & LOCK;
>> > > > if(bit ==0x00)
>> > > > goto Lock_loop;
>> > > >
>> > > > CLKSEL=0x80; /* CLK=PLLCLK */
>> > > > CRGFLG=0x10; /* LOCKIF Cleared */
>> > > >
>> > > > 3) above code is tested for input clk = 10mhz and bus clk is
>> comming >> > > 2.5 mhz
>> > > > 4)for this filter compnent on XFC are as follow
>> > > > Rc7 OHM
>> > > > cs= 81 nf
>> > > > cp=8.1 nf
>> > > > so i put rc4 ohm..cs0nf...cp= 10 nf
>> > > >
>> > > > After this the Bus clock is not comming so kindly give your
>> suggestion
>> > > if any thing i had miissed out.
>> > > > For your information with 10mhz clk source ,2.5 mhz was comming at
>> that
>> > > time RS = 622 CS 100 NF AND CP NF
>> > > >
>> > > > Imtiyaz
>> > > >
>> > >
>> > >
>> > >
>> >
>> >
>> >
>> >
>>
>>
>>