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Hi, I want to implement a shadow RAM ,for holding my data in the EEPROM. So my requirement is to have some portion of the RAM mapped to EEPROM locations so that ,it will always have the contents of EEPROM .So this allows me to avoid the frequent reading of EEPROM and to write modified values need to change it only in the shadow RAM area and this will get updated to the EEPROM via a low priority task . It would be great if anyone suggest how can achieve this the mapping of EEPROM to a RAM location with DP256 and Metrowerks compiler /linker suite.Is any linker directives is there to get the things done automatically?. Any help is greatly appreciated. Regards Vibin |
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Mapping EEPROM to RAM
Started by ●July 7, 2003
Reply by ●July 7, 20032003-07-07
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Hi Vibin, There is not an elegant way to do this using the DP256. If you relocate the RAM so that it is mapped over the EEPROM, on-chip hardware ensures that the RAM take precedence. The method to write to EEPROM is very different to the method to write to RAM, and you will end up writing a function to copy down the data stored in EEPROM to RAM. Your scheduler will also need to copy the RAM back to EEPROM periodically. What it sounds that you really need is the MC9S12T64, that has a 2k calibration RAM. Check this out on the Motorola website at http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MC9S12T64 <http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MC9S12T64&nodeIdt3ZGpnLn8636K100> &nodeIdt3ZGpnLn8636K100 KR, Mark The information contained in this communication has been classified as: ( X) General Business Information ( ) Motorola & Distributor Internal Use Only ( ) Motorola Confidential Proprietary -----Original Message----- From: vvibin2003 [mailto:] Sent: 07 July 2003 14:41 To: Subject: [68HC12] Mapping EEPROM to RAM Hi, I want to implement a shadow RAM ,for holding my data in the EEPROM. So my requirement is to have some portion of the RAM mapped to EEPROM locations so that ,it will always have the contents of EEPROM .So this allows me to avoid the frequent reading of EEPROM and to write modified values need to change it only in the shadow RAM area and this will get updated to the EEPROM via a low priority task . It would be great if anyone suggest how can achieve this the mapping of EEPROM to a RAM location with DP256 and Metrowerks compiler /linker suite.Is any linker directives is there to get the things done automatically?. Any help is greatly appreciated. Regards Vibin Yahoo! Groups Sponsor <http://hits.411web.com/cgi-bin/autoredir?campU6&lineid512844&prop=egroupweb&pos=HM>" target="_blank" rel="nofollow">http://rd.yahoo.com/M$9982.3512844.4795476.1261774/D=egroupweb/S06554205:HM/A24963/R=0/SIGo72ctft/*http://hits.411web.com/cgi-bin/autoredir?campU6&lineid512844&prop=egroupweb&pos=HM> <http://us.adserver.yahoo.com/l?M$9982.3512844.4795476.1261774/D=egroupmail/S=:HM/A24963/randd5101411> -------------------- <http://www.motorola.com/mcu ">http://docs.yahoo.com/info/terms/> . |
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Reply by ●July 7, 20032003-07-07
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Actually, there probably is a way, but by the time you: 1) figure it out. 2) code it. 3) test it. 4) fix it. 5) retest it. 6) document it so that the next programmer can follow what you did. you could brute-force it in half the time. By the way, don't forget to figure out what to do if there is a power failure or reset during the update cycle. At least add a marker flag so that the process will know that the data may not be OK. Gary Olmstead Toucan Technology Ventura CA At 01:40 PM 7/7/03 +0000, you wrote: >Hi, > > I want to implement a shadow RAM ,for holding my data in the EEPROM. >So my requirement is to have some portion of the RAM mapped to EEPROM >locations so that ,it will always have the contents of EEPROM .So >this allows me to avoid the frequent reading of EEPROM and to write >modified values need to change it only in the shadow RAM area and >this will get updated to the EEPROM via a low priority task . >It would be great if anyone suggest how can achieve this the mapping >of EEPROM to a RAM location with DP256 and Metrowerks >compiler /linker suite.Is any linker directives is there to get the >things done automatically?. > >Any help is greatly appreciated. >Regards >Vibin > > >-------------------- > >">http://docs.yahoo.com/info/terms/ > |
Reply by ●July 7, 20032003-07-07
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I checked out the website re. S12T64, so now I wonder what is flash
EEPROM (my 12 has flash and EEPROM), and what is a CALRAM. I searched the site to no effect. Thanks, Bob White ----- Original Message ----- From: "Dunnett Mark-R60287" <> To: <> Sent: Monday, July 07, 2003 7:24 AM Subject: RE: [68HC12] Mapping EEPROM to RAM > Hi Vibin, > > There is not an elegant way to do this using the DP256. If you relocate the RAM so that it is mapped over the EEPROM, on-chip hardware ensures that the RAM take precedence. The method to write to EEPROM is very different to the method to write to RAM, and you will end up writing a function to copy down the data stored in EEPROM to RAM. Your scheduler will also need to copy the RAM back to EEPROM periodically. > > What it sounds that you really need is the MC9S12T64, that has a 2k calibration RAM. Check this out on the Motorola website at > > http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MC9S12T64 <http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MC9S12T64&n odeIdt3ZGpnLn8636K100> &nodeIdt3ZGpnLn8636K100 > > > KR, > > Mark > > The information contained in this communication has been classified as: > ( X) General Business Information > ( ) Motorola & Distributor Internal Use Only > ( ) Motorola Confidential Proprietary > -----Original Message----- > From: vvibin2003 [mailto:] > Sent: 07 July 2003 14:41 > To: > Subject: [68HC12] Mapping EEPROM to RAM > Hi, > > I want to implement a shadow RAM ,for holding my data in the EEPROM. > So my requirement is to have some portion of the RAM mapped to EEPROM > locations so that ,it will always have the contents of EEPROM .So > this allows me to avoid the frequent reading of EEPROM and to write > modified values need to change it only in the shadow RAM area and > this will get updated to the EEPROM via a low priority task . > It would be great if anyone suggest how can achieve this the mapping > of EEPROM to a RAM location with DP256 and Metrowerks > compiler /linker suite.Is any linker directives is there to get the > things done automatically?. > > Any help is greatly appreciated. > Regards > Vibin > > > Yahoo! Groups Sponsor > <http://rd.yahoo.com/M$9982.3512844.4795476.1261774/D=egroupweb/S065542 05:HM/A24963/R=0/SIGo72ctft/*http://hits.411web.com/cgi-bin/autoredir? campU6&lineid512844&prop=egroupweb&pos=HM> > <http://us.adserver.yahoo.com/l?M$9982.3512844.4795476.1261774/D=egroupmai l/S=:HM/A24963/randd5101411> > > -------------------- > <http://www.motorola.com/mcu > ">http://docs.yahoo.com/info/terms/> . > > -------------------- > > ">http://docs.yahoo.com/info/terms/ > |
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Reply by ●July 7, 20032003-07-07
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Flash EEPROM is what you call in simple words Flash. CALRAM is Calibration RAM that you can place over the 2K portion of Flash that you want to Erase and Re-program, in order be able to continue to access this portion of Flash (in the CALRAM) during the execution of your Erase and Re-program algorithms. The CALRAM is 2KByte in size and may be placed anywhere in the address map using the INITCRM register, and independent of the location of the traditional RAM (2KByte in size also) that follows the INITRM register. The INITCRM register is also "many times writable" and has an additional enable bit that may remove the CALRAM from the map, so the CALRAM may be enabled, disabled and replaced in the address map an unlimited number of times (and not just one time like in the case of the INITRM register). Hope this helps, Doron Nohau Corporation HC12 In-Circuit Emulators www.nohau.com/emul12pc.html At 08:30 AM 7/7/2003 -0700, you wrote: >I checked out the website re. S12T64, so now I wonder what is flash EEPROM >(my 12 has flash and EEPROM), and what is a CALRAM. I searched the site to >no effect. >Thanks, >Bob White > >----- Original Message ----- >From: "Dunnett Mark-R60287" <> >To: <> >Sent: Monday, July 07, 2003 7:24 AM >Subject: RE: [68HC12] Mapping EEPROM to RAM > > Hi Vibin, > > > > There is not an elegant way to do this using the DP256. If you relocate >the RAM so that it is mapped over the EEPROM, on-chip hardware ensures that >the RAM take precedence. The method to write to EEPROM is very different to >the method to write to RAM, and you will end up writing a function to copy >down the data stored in EEPROM to RAM. Your scheduler will also need to copy >the RAM back to EEPROM periodically. > > > > What it sounds that you really need is the MC9S12T64, that has a 2k >calibration RAM. Check this out on the Motorola website at > > > > http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MC9S12T64 ><http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MC9S12T64&n >odeIdt3ZGpnLn8636K100> &nodeIdt3ZGpnLn8636K100 > > > > > > KR, > > > > Mark > > > > The information contained in this communication has been classified as: > > ( X) General Business Information > > ( ) Motorola & Distributor Internal Use Only > > ( ) Motorola Confidential Proprietary > > > > > > -----Original Message----- > > From: vvibin2003 [mailto:] > > Sent: 07 July 2003 14:41 > > To: > > Subject: [68HC12] Mapping EEPROM to RAM > > > > > > Hi, > > > > I want to implement a shadow RAM ,for holding my data in the EEPROM. > > So my requirement is to have some portion of the RAM mapped to EEPROM > > locations so that ,it will always have the contents of EEPROM .So > > this allows me to avoid the frequent reading of EEPROM and to write > > modified values need to change it only in the shadow RAM area and > > this will get updated to the EEPROM via a low priority task . > > It would be great if anyone suggest how can achieve this the mapping > > of EEPROM to a RAM location with DP256 and Metrowerks > > compiler /linker suite.Is any linker directives is there to get the > > things done automatically?. > > > > Any help is greatly appreciated. > > Regards > > Vibin > > |
Reply by ●July 7, 20032003-07-07
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Hi all, Thanks to all for your time. But I have to use DP256 and no other go at this moment.And my application is multithreaded,and to ensure a problem free EEPROM access,i prefered to have a shadow RAM ,which will be a copy of EEPROM data and this will avoid the need to have frequent EEPROM Read/Writes which steals a good amount of CPU cycles.From the data sheet it's found that a sector write in EEPROM takes 20-20ms and during this time I need to ensure no EEPROM reads are done!!!!) So from your feedback my understanding is I have to manually copy the contents of EEPROM to a location in RAM,to be identified as shadow RAM and that has to be done periodically.And my assumption of mapping EEPROM to RAM location will not work out with DP256 or H256(Mako). Am I right?. Best Regards Vibin --- In , Dunnett Mark-R60287 <mark.dunnett@m...> wrote: > Hi Vibin, > > There is not an elegant way to do this using the DP256. If you relocate the RAM so that it is mapped over the EEPROM, on-chip hardware ensures that the RAM take precedence. The method to write to EEPROM is very different to the method to write to RAM, and you will end up writing a function to copy down the data stored in EEPROM to RAM. Your scheduler will also need to copy the RAM back to EEPROM periodically. > > What it sounds that you really need is the MC9S12T64, that has a 2k calibration RAM. Check this out on the Motorola website at > > http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp? code=MC9S12T64 <http://e- www.motorola.com/webapp/sps/site/prod_summary.jsp? code=MC9S12T64&nodeIdt3ZGpnLn8636K100> &nodeIdt3ZGpnLn8636K100 > > > KR, > > Mark > > The information contained in this communication has been classified as: > ( X) General Business Information > ( ) Motorola & Distributor Internal Use Only > ( ) Motorola Confidential Proprietary > -----Original Message----- > From: vvibin2003 [mailto:vvibin2003@y...] > Sent: 07 July 2003 14:41 > To: > Subject: [68HC12] Mapping EEPROM to RAM > Hi, > > I want to implement a shadow RAM ,for holding my data in the EEPROM. > So my requirement is to have some portion of the RAM mapped to EEPROM > locations so that ,it will always have the contents of EEPROM .So > this allows me to avoid the frequent reading of EEPROM and to write > modified values need to change it only in the shadow RAM area and > this will get updated to the EEPROM via a low priority task . > It would be great if anyone suggest how can achieve this the mapping > of EEPROM to a RAM location with DP256 and Metrowerks > compiler /linker suite.Is any linker directives is there to get the > things done automatically?. > > Any help is greatly appreciated. > Regards > Vibin > > > Yahoo! Groups Sponsor > <http://rd.yahoo.com/M$9982.3512844.4795476.1261774/D=egroupweb/S 06554205:HM/A24963/R=0/SIGo72ctft/*http://hits.411web.com/cgi- bin/autoredir?campU6&lineid512844&prop=egroupweb&pos=HM> > <http://us.adserver.yahoo.com/l? M$9982.3512844.4795476.1261774/D=egroupmail/S=:HM/A24963/randd5 101411> > > -------------------- > <http://www.motorola.com/mcu > ">http://docs.yahoo.com/info/terms/> . > |
Reply by ●July 8, 20032003-07-08
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It need not be quite as hard work as that. Yes copy the EEPROM to RAM. Split in half, with a check sum in each half. If the first check sum is wrong then copy the second half over the first half. If the second half check sum is also wrong, then unusually your data is corrupted. After writing a data to RAM image (which is half the size of the EEPROM - 1), generate a check sum then compare byte for byte the RAM with EEPROM and only program the differences. Then do this a second time for second half. This system is very robust, a little more complicated to code, but processor overhead is small. If you attempt handling this by interrupt you may spoil the system's robustness. Andrew Lohmann AIIE Design Engineer Bellingham + Stanley Ltd. Longfield Road, Tunbridge Wells, Kent, TN2 3EY, England. Tel: +44 (0) 1892 500400 Fax: +44 (0) 1892 543115 Website: www.bs-ltd.com ----- Original Message ----- From: "vvibin2003" <> To: <> Sent: Tuesday, July 08, 2003 4:58 AM Subject: [68HC12] Re: Mapping EEPROM to RAM > Hi all, > > Thanks to all for your time. > > But I have to use DP256 and no other go at this moment.And my > application is multithreaded,and to ensure a problem free EEPROM > access,i prefered to have a shadow RAM ,which will be a copy of > EEPROM data and this will avoid the need to have frequent EEPROM > Read/Writes which steals a good amount of CPU cycles.From the > data sheet it's found that a sector write in EEPROM takes 20-20ms > and during this time I need to ensure no EEPROM reads are done!!!!) > > So from your feedback my understanding is I have to manually > copy the contents of EEPROM to a location in RAM,to be identified > as shadow RAM and that has to be done periodically.And my > assumption of mapping EEPROM to RAM location will not work out > with DP256 or H256(Mako). Am I right?. > > Best Regards > Vibin > > --- In , Dunnett Mark-R60287 > <mark.dunnett@m...> wrote: > > Hi Vibin, > > > > There is not an elegant way to do this using the DP256. If you > relocate the RAM so that it is mapped over the EEPROM, on-chip > hardware ensures that the RAM take precedence. The method to write to > EEPROM is very different to the method to write to RAM, and you will > end up writing a function to copy down the data stored in EEPROM to > RAM. Your scheduler will also need to copy the RAM back to EEPROM > periodically. > > > > What it sounds that you really need is the MC9S12T64, that has a 2k > calibration RAM. Check this out on the Motorola website at > > > > http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp? > code=MC9S12T64 <http://e- > www.motorola.com/webapp/sps/site/prod_summary.jsp? > code=MC9S12T64&nodeIdt3ZGpnLn8636K100> &nodeIdt3ZGpnLn8636K100 > > > > > > KR, > > > > Mark > > > > The information contained in this communication has been classified > as: > > ( X) General Business Information > > ( ) Motorola & Distributor Internal Use Only > > ( ) Motorola Confidential Proprietary > > > > > > -----Original Message----- > > From: vvibin2003 [mailto:vvibin2003@y...] > > Sent: 07 July 2003 14:41 > > To: > > Subject: [68HC12] Mapping EEPROM to RAM > > > > > > Hi, > > > > I want to implement a shadow RAM ,for holding my data in the > EEPROM. > > So my requirement is to have some portion of the RAM mapped to > EEPROM > > locations so that ,it will always have the contents of EEPROM .So > > this allows me to avoid the frequent reading of EEPROM and to write > > modified values need to change it only in the shadow RAM area and > > this will get updated to the EEPROM via a low priority task . > > It would be great if anyone suggest how can achieve this the > mapping > > of EEPROM to a RAM location with DP256 and Metrowerks > > compiler /linker suite.Is any linker directives is there to get the > > things done automatically?. > > > > Any help is greatly appreciated. > > Regards > > Vibin > > > > > > > > > > Yahoo! Groups Sponsor > > > <http://rd.yahoo.com/M$9982.3512844.4795476.1261774/D=egroupweb/S > 06554205:HM/A24963/R=0/SIGo72ctft/*http://hits.411web.com/cgi- > bin/autoredir?campU6&lineid512844&prop=egroupweb&pos=HM> > > <http://us.adserver.yahoo.com/l? > M$9982.3512844.4795476.1261774/D=egroupmail/S=:HM/A24963/randd5 > 101411> > > > > -------------------- > > <http://www.motorola.com/mcu> > > > > > > ">http://docs.yahoo.com/info/terms/> . > > > > > > > > > -------------------- > > ">http://docs.yahoo.com/info/terms/ > > > --- Email Disclaimer --- > > Internet communications are not secure and therefore Bellingham + Stanley Ltd does > not accept legal responsibility for the contents of this message. Any views > or opinions presented are solely those of the author and do not necessarily > represent those of Bellingham + Stanley Ltd unless otherwise specifically stated. > If this message is received by anyone other than the addressee, please > notify the sender and then delete the message and any attachments from your > computer. > > --- End --- > --- Email Disclaimer --- Internet communications are not secure and therefore Bellingham + Stanley Ltd does not accept legal responsibility for the contents of this message. Any views or opinions presented are solely those of the author and do not necessarily represent those of Bellingham + Stanley Ltd unless otherwise specifically stated. If this message is received by anyone other than the addressee, please notify the sender and then delete the message and any attachments from your computer. --- End --- |
Reply by ●July 8, 20032003-07-08
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Nice approach. One thought - the checksum algorithm should be chosen such that an erased block of flash does not pass (eg, sum to $FFFF). Otherwise you are vulnerable to a block that was erased but never programmed. 607-656-2597 -----Original Message----- From: Andrew Lohmann's New Email Server [mailto:] Sent: Tuesday, July 08, 2003 4:03 AM To: Subject: Re: [68HC12] Re: Mapping EEPROM to RAM It need not be quite as hard work as that. Yes copy the EEPROM to RAM. Split in half, with a check sum in each half. If the first check sum is wrong then copy the second half over the first half. If the second half check sum is also wrong, then unusually your data is corrupted. After writing a data to RAM image (which is half the size of the EEPROM - 1), generate a check sum then compare byte for byte the RAM with EEPROM and only program the differences. Then do this a second time for second half. This system is very robust, a little more complicated to code, but processor overhead is small. If you attempt handling this by interrupt you may spoil the system's robustness. Andrew Lohmann AIIE Design Engineer Bellingham + Stanley Ltd. Longfield Road, Tunbridge Wells, Kent, TN2 3EY, England. Tel: +44 (0) 1892 500400 Fax: +44 (0) 1892 543115 Website: www.bs-ltd.com ----- Original Message ----- From: "vvibin2003" <> To: <> Sent: Tuesday, July 08, 2003 4:58 AM Subject: [68HC12] Re: Mapping EEPROM to RAM > Hi all, > > Thanks to all for your time. > > But I have to use DP256 and no other go at this moment.And my > application is multithreaded,and to ensure a problem free EEPROM > access,i prefered to have a shadow RAM ,which will be a copy of > EEPROM data and this will avoid the need to have frequent EEPROM > Read/Writes which steals a good amount of CPU cycles.From the > data sheet it's found that a sector write in EEPROM takes 20-20ms > and during this time I need to ensure no EEPROM reads are done!!!!) > > So from your feedback my understanding is I have to manually > copy the contents of EEPROM to a location in RAM,to be identified > as shadow RAM and that has to be done periodically.And my > assumption of mapping EEPROM to RAM location will not work out > with DP256 or H256(Mako). Am I right?. > > Best Regards > Vibin > > --- In , Dunnett Mark-R60287 > <mark.dunnett@m...> wrote: > > Hi Vibin, > > > > There is not an elegant way to do this using the DP256. If you > relocate the RAM so that it is mapped over the EEPROM, on-chip > hardware ensures that the RAM take precedence. The method to write to > EEPROM is very different to the method to write to RAM, and you will > end up writing a function to copy down the data stored in EEPROM to > RAM. Your scheduler will also need to copy the RAM back to EEPROM > periodically. > > > > What it sounds that you really need is the MC9S12T64, that has a 2k > calibration RAM. Check this out on the Motorola website at > > > > http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp? > code=MC9S12T64 <http://e- > www.motorola.com/webapp/sps/site/prod_summary.jsp? > code=MC9S12T64&nodeIdt3ZGpnLn8636K100> &nodeIdt3ZGpnLn8636K100 > > > > > > KR, > > > > Mark > > > > The information contained in this communication has been classified > as: > > ( X) General Business Information > > ( ) Motorola & Distributor Internal Use Only > > ( ) Motorola Confidential Proprietary > > > > > > -----Original Message----- > > From: vvibin2003 [mailto:vvibin2003@y...] > > Sent: 07 July 2003 14:41 > > To: > > Subject: [68HC12] Mapping EEPROM to RAM > > > > > > Hi, > > > > I want to implement a shadow RAM ,for holding my data in the > EEPROM. > > So my requirement is to have some portion of the RAM mapped to > EEPROM > > locations so that ,it will always have the contents of EEPROM .So > > this allows me to avoid the frequent reading of EEPROM and to write > > modified values need to change it only in the shadow RAM area and > > this will get updated to the EEPROM via a low priority task . > > It would be great if anyone suggest how can achieve this the > mapping > > of EEPROM to a RAM location with DP256 and Metrowerks > > compiler /linker suite.Is any linker directives is there to get the > > things done automatically?. > > > > Any help is greatly appreciated. > > Regards > > Vibin > > > > > > > > > > Yahoo! Groups Sponsor > > > <http://rd.yahoo.com/M$9982.3512844.4795476.1261774/D=egroupweb/S > 06554205:HM/A24963/R=0/SIGo72ctft/*http://hits.411web.com/cgi- > bin/autoredir?campU6&lineid512844&prop=egroupweb&pos=HM> > > <http://us.adserver.yahoo.com/l? > M$9982.3512844.4795476.1261774/D=egroupmail/S=:HM/A24963/randd5 > 101411> > > > > -------------------- > > <http://www.motorola.com/mcu> > > > > > > ">http://docs.yahoo.com/info/terms/> . > > > > > > > > > -------------------- > > ">http://docs.yahoo.com/info/terms/ > > > --- Email Disclaimer --- > > Internet communications are not secure and therefore Bellingham + Stanley Ltd does > not accept legal responsibility for the contents of this message. Any views > or opinions presented are solely those of the author and do not necessarily > represent those of Bellingham + Stanley Ltd unless otherwise specifically stated. > If this message is received by anyone other than the addressee, please > notify the sender and then delete the message and any attachments from your > computer. > > --- End --- > --- Email Disclaimer --- Internet communications are not secure and therefore Bellingham + Stanley Ltd does not accept legal responsibility for the contents of this message. Any views or opinions presented are solely those of the author and do not necessarily represent those of Bellingham + Stanley Ltd unless otherwise specifically stated. If this message is received by anyone other than the addressee, please notify the sender and then delete the message and any attachments from your computer. --- End --- -------------------- ">http://docs.yahoo.com/info/terms/ |
Reply by ●July 8, 20032003-07-08
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Hi, Has anyone tried keeping the SRAM alive during power down mode, using a dedicated SRAM power pin to a super cap etc. Normally you would just checksum the data after writing to it. Can the SRAM on the DP256 series be powered without powering the rest of the core? Fred ----- Original Message ----- From: Doron Fael To: Sent: Monday, July 07, 2003 11:10 AM Subject: Re: [68HC12] Mapping EEPROM to RAM Flash EEPROM is what you call in simple words Flash. CALRAM is Calibration RAM that you can place over the 2K portion of Flash that you want to Erase and Re-program, in order be able to continue to access this portion of Flash (in the CALRAM) during the execution of your Erase and Re-program algorithms. The CALRAM is 2KByte in size and may be placed anywhere in the address map using the INITCRM register, and independent of the location of the traditional RAM (2KByte in size also) that follows the INITRM register. The INITCRM register is also "many times writable" and has an additional enable bit that may remove the CALRAM from the map, so the CALRAM may be enabled, disabled and replaced in the address map an unlimited number of times (and not just one time like in the case of the INITRM register). Hope this helps, Doron Nohau Corporation HC12 In-Circuit Emulators www.nohau.com/emul12pc.html At 08:30 AM 7/7/2003 -0700, you wrote: >I checked out the website re. S12T64, so now I wonder what is flash EEPROM >(my 12 has flash and EEPROM), and what is a CALRAM. I searched the site to >no effect. >Thanks, >Bob White > >----- Original Message ----- >From: "Dunnett Mark-R60287" <> >To: <> >Sent: Monday, July 07, 2003 7:24 AM >Subject: RE: [68HC12] Mapping EEPROM to RAM > > Hi Vibin, > > > > There is not an elegant way to do this using the DP256. If you relocate >the RAM so that it is mapped over the EEPROM, on-chip hardware ensures that >the RAM take precedence. The method to write to EEPROM is very different to >the method to write to RAM, and you will end up writing a function to copy >down the data stored in EEPROM to RAM. Your scheduler will also need to copy >the RAM back to EEPROM periodically. > > > > What it sounds that you really need is the MC9S12T64, that has a 2k >calibration RAM. Check this out on the Motorola website at > > > > http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MC9S12T64 ><http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MC9S12T64&n >odeIdt3ZGpnLn8636K100> &nodeIdt3ZGpnLn8636K100 > > > > > > KR, > > > > Mark > > > > The information contained in this communication has been classified as: > > ( X) General Business Information > > ( ) Motorola & Distributor Internal Use Only > > ( ) Motorola Confidential Proprietary > > > > > > -----Original Message----- > > From: vvibin2003 [mailto:] > > Sent: 07 July 2003 14:41 > > To: > > Subject: [68HC12] Mapping EEPROM to RAM > > > > > > Hi, > > > > I want to implement a shadow RAM ,for holding my data in the EEPROM. > > So my requirement is to have some portion of the RAM mapped to EEPROM > > locations so that ,it will always have the contents of EEPROM .So > > this allows me to avoid the frequent reading of EEPROM and to write > > modified values need to change it only in the shadow RAM area and > > this will get updated to the EEPROM via a low priority task . > > It would be great if anyone suggest how can achieve this the mapping > > of EEPROM to a RAM location with DP256 and Metrowerks > > compiler /linker suite.Is any linker directives is there to get the > > things done automatically?. > > > > Any help is greatly appreciated. > > Regards > > Vibin > > -------------------- |
