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I have calculated the BR value and programmed the SCI for different rates without problem, but I haven't found a maximum rate specified. I sort of assumed it was limited by the BR register, but I have not been able to get 115.2k to work. Has anyone else? Does anyone know the max rate? Thanks code: ; Serial I/O Setup ; Using notes from Mot: ; SCI Baud Rate = SCI module clock / (16 * BR) ; where BR is the combination of BDL and BDH ; the SCI module clock is 4MHz (3993600 Hz) ;Desired BAUD SCIBRR SCIBRR Hex ; 1200 208 D0 ; 2400 104 68 ; 4800 52 34 ; 9600 26 1A ; 19200 13 0D ;115200 2.17 02 CLR SCIBDH LDAB #$0D STAB SCIBDL ; sets it for 19.2k |
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HCS12 maximum SCI rate?
Started by ●July 16, 2004
Reply by ●July 16, 20042004-07-16
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--- In , "big_bear_london" <big_bear_london@y...> wrote: > I have calculated the BR value and programmed the SCI for different > rates without problem, but I haven't found a maximum rate specified. > I sort of assumed it was limited by the BR register, but I have not > been able to get 115.2k to work. Has anyone else? Does anyone know > the max rate? Depens on your clock speed, after dividing by a whole number you will have an error in the desired Baud rate, when error gets to high she no work no more. Cheers, Theo |
Reply by ●July 16, 20042004-07-16
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If you are using a 9s12, PLL your 4mHz crystal up up to 24mHz. Your baudrate divisor then becomes 24mHz/16/baud_rate which works out to be very close to decimal 13 for 115200 baud. I have a design that runs both serial ports almost constantly at 115200 baud with ease. Rounding your 4 mHz derived divisor from the ideal "2.17" to "2" probably puts your actual baudrate too far off the mark for standard PC UARTS, if that's what you're talking to. If you need very exact baud rates you can PLL a 3.686 mHz xtal up to around 22.118 mHz, which yields an exact divisor of 12 for 115200 baud and allows exact baud rates as high as 460800, which is probably the practical limit for a typical system in view of software overhead needed to service the comm port. If you are using a slower processor or one without a PLL, just use a standard "baud rate" crystal like 14.7 mHz, 7.37 mHz, etc. as you your CPU clock. Bill Tondreau http://www.kupercontrols.com <big_bear_london@y...> wrote: > I have calculated the BR value and programmed the SCI for different > rates without problem, but I haven't found a maximum rate specified. > I sort of assumed it was limited by the BR register, but I have not > been able to get 115.2k to work. Has anyone else? Does anyone know > the max rate? > > Thanks > > code: > > ; Serial I/O Setup > ; Using notes from Mot: > ; SCI Baud Rate = SCI module clock / (16 * BR) > ; where BR is the combination of BDL and BDH > ; the SCI module clock is 4MHz (3993600 Hz) > > ;Desired BAUD SCIBRR SCIBRR Hex > ; 1200 208 D0 > ; 2400 104 68 > ; 4800 52 34 > ; 9600 26 1A > ; 19200 13 0D > ;115200 2.17 02 > > CLR SCIBDH > LDAB #$0D > STAB SCIBDL ; sets it for 19.2k |
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Reply by ●July 20, 20042004-07-20
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Rule of thumb: Baud rates need to match within 5% in order to work. The common 8-N-1, 7-E-1, and 7-O-1 data words all send 10 bits of data for each byte transmitted. If the receiving UART samples exactly in the middle of the start bit, that means that the clocks can drift up to half a bit by the end of the word without corrupting the stop bit. Half a bit, out of ten bits, is 5%. Thus the clocks need to match within 5%. There are lots of refinements one could make, but ultimately, whether it is off by half a percent one way or the other is unimportant. A robust design will stay well under 5%. Keep in mind that the 5% is for both ends of the link. I keep to half of that (2.5% or better) when I pick baud divisors, because whatever is at the other end of the line might need some of the margin, too. Stephen -- Stephen Trier Technical Development Lab Cleveland FES Center |
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Reply by ●July 20, 20042004-07-20
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At 11:20 AM 7/20/2004, Stephen Trier wrote: >There are lots of refinements one could make, but ultimately, whether it >is off by half a percent one way or the other is unimportant. A robust >design will stay well under 5%. > >Keep in mind that the 5% is for both ends of the link. I keep to half >of that (2.5% or better) when I pick baud divisors, because whatever is >at the other end of the line might need some of the margin, too. If the connection is long or noisy you should probably consider some analog filtering between the connection and the receive pin. If EMC is a consideration, you may want some analog filtering on the transmit pin for "slope control". These filters and the effects of noise will add distortion, include them in your analysis of how close the clocks have to be. I agree that 1% per end should be good enough in bad cases, but 2.5% per end definitely won't work in the presence of noise and aggressive filtering. |
