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9S12DP256 CAN Initialization

Started by bdcps2002 ●September 10, 2002
Hi everybody,
I am using MC9S12DP256 on TechnologicalArts board, which has 2 CAN
ports. Even though CAN works in Loopback mode, I couldn't get them to
talk to each other.
When initializing, do I have to do anything other than:

// Enable MSCAN module.???? Anything else to seperate it from
// being used as general I/0
CAN0CTL1 |= 0x80;
// set SFTRES to place CAN module in reset (initialization)
CAN0CTL0 |= 1;
// clear Listen Only Mode
CAN0CTL1 &= 0xEF;
// Enable timers
CAN0CTL0 |= 0x08;

// Enable Loopback
//CAN0CTL1 |= 0x20;

CAN0BTR0=0xC1;
CAN0BTR1 = 0x4C;
CAN0IDMR0 = 0xFF;

CAN0IDMR1 = 0xFF;
CAN0IDMR2 = 0xFF;
CAN0IDMR3 = 0xFF;

CAN0RIER = 0;
CAN0TIER = 0;

CAN0CTL0 &=~1;
while (!(CAN0CTL0 & 0x10));

Thanks a lot for any insights.
Dzung.


Reply by Steve Letkeman ●September 10, 20022002-09-10
This should help you out a bit

Steve

Zanthic Technologies Inc. is located at www.zanthic.com
Your Controller Area Networking Experts!
Embedded micro-controllers and CAN interface devices sold here // This file may be freely distributed as long as this header remains
// intact in order to encourage you to visit our web site at www.zanthic.com

// This simple program was written as a quick and easy
// example of initializing and testing the msCAN port
// on an HC912BC32 processor.
// This program was written as a single file for
// simplicity and only some of the registers are included.
// Written by Steve Letkeman Feb 2001

// compiled using the ICC12 compiler from imagecraft (www.imagecraft.com)
// and tested on the CME-12BC32 development board from Axiom (www.axman.com)

#include <hc12.h>
//#include "vectors.c"
void CANInit(void);

#define _CAN_BASE 0x0100 // CAN Base Address
#define _CP(off) *(unsigned char volatile *)(_CAN_BASE + off)

#define CMCR0 _CP(0) // Control Register 0
#define CMCR1 _CP(1) // Control Register 1
#define CBTR0 _CP(2) // Bus Timing Register 0
#define CBTR1 _CP(3) // Bus Timing Register 1
#define CRFLG _CP(4) // Receiver Flag Register
#define CRIER _CP(5) // Receiver Interrupt Enable Register
#define CTFLG _CP(6) // Transmitter Flag Register
#define CTCR _CP(7) // Transmitter Control Register
#define CIDAC _CP(8) // Identifier Acceptance Control Register
#define CRXERR _CP(0x0E) // Receive Error Counter
#define CTXERR _CP(0x0F) // Transmitter Error Counter
#define CIDAR0 _CP(0x10) // Acceptance Register 0
#define CIDAR1 _CP(0x11) // Acceptance Register 1
#define CIDAR2 _CP(0x12) // Acceptance Register 2
#define CIDAR3 _CP(0x13) // Acceptance Register 3
#define CIDMR0 _CP(0x14) // Identifier Mask Register 0
#define CIDMR1 _CP(0x15) // Identifier Mask Register 1
#define CIDMR2 _CP(0x16) // Identifier Mask Register 2
#define CIDMR3 _CP(0x17) // Identifier Mask Register 3
#define CIDAR4 _CP(0x18) // Acceptance Register 4
#define CIDAR5 _CP(0x19) // Acceptance Register 5
#define CIDAR6 _CP(0x1A) // Acceptance Register 6
#define CIDAR7 _CP(0x1B) // Acceptance Register 7
#define CIDMR4 _CP(0x1C) // Identifier Mask Register 4
#define CIDMR5 _CP(0x1D) // Identifier Mask Register 5
#define CIDMR6 _CP(0x1E) // Identifier Mask Register 6
#define CIDMR7 _CP(0x1F) // Identifier Mask Register 7
#define PCTLCAN _CP(0x3D) // Control Register
#define PORTCAN _CP(0x3E) // Data Register
#define DDRCAN _CP(0x3F) // Data Direction Register
// from page 129 68HC912BC32.pdf

#define RXIDR0 _CP(0x40) // first byte of ID for the receive buffer
#define RXIDR1 _CP(0x41) // 2nd byte of ID for the receive buffer
#define RXIDR2 _CP(0x42) // 3rd byte of ID for the receive buffer
#define RXIDR3 _CP(0x43) // 4th byte of ID for the receive buffer
#define RXDSR0 _CP(0x44) // first byte of data for the receive buffer
#define RXDLR _CP(0x4C) // Data Length (number of bytes received)

// create defines for the first transmit message object. The
// other 2 are not defined
#define TX0IDR0 _CP(0x50) // first byte of ID for the transmit buffer 0
#define TX0IDR1 _CP(0x51) // second byte of ID for the transmit buffer 0
#define TX0IDR2 _CP(0x52) // third byte of ID for the transmit buffer 0
#define TX0IDR3 _CP(0x53) // fourth byte of ID for the transmit buffer 0
#define TX0DSR0 _CP(0x54) // first byte of data
#define TX0DSR1 _CP(0x55) // second byte of data...3-8 are left to you
#define TX0DLR _CP(0x5C) // Data Length Register
#define TX0PRI _CP(0x5D) // Priority

#define TBPR _CP(0xBD) // Transmit Buffer Priority Registers

void main()
{
unsigned char x;
setbaud(BAUD9600); // initialize serial port for text output
printf("CAN Test Program\n");

COPCTL=0; // turn off watchdog
CANInit(); // initial CAN port

printf("transmitting a message\n");
TX0IDR0=0xAA; // 29 bit ID with 1010 pattern for all 29 bits
TX0IDR1=0xAA; // 29 bit is defined by setting bit 3
TX0IDR2=0xAA;
TX0IDR3=0xAA;
TX0DSR0=0x55; // first byte of data
TX0DSR1=0x66; // second byte of data
TX0DLR=0x02; // set to send 2 bytes of data

while(!(CTFLG & 1)); //wait until Tx buffer is available
CTFLG = 1; //transmit
printf("Message transmitted\n");
printf("Transmit error counter =%d\n",CTXERR); // check for errors

while(1)
{
printf("\nwaiting for incoming CAN message\n");
while(!(CRFLG & 1)); //wait for CAN incoming CAN message
printf("Received a message!\n");
printf("ID Registers=%X-%X-%X-%X\n",RXIDR0,RXIDR1,RXIDR2,RXIDR3);
if (RXIDR1 & 8) printf("This was a 29 bit message");
else printf("This was an 11 bit message");
printf(" with %d bytes of data\n",RXDLR & 0x0F);
printf("Data=");
for (x=0;x<(RXDLR&0x0F);x++) // loop through data
printf("%X ",RXDSR0+x);
printf("\n");

CRFLG |=1; // clear rec flag

// transmit the initial message again
while(!(CTFLG & 1)); //wait until Tx buffer is available
CTFLG=1;
}
}

void CANInit(void)
{
// the following two lines only apply to the Axiom HC12 board
DDRCAN |=4; // turn on bit 2 which is connected to pin 8 of 82C250
PORTCAN &=~4; // clear bit to enable
CMCR0 |=1; // set SFTRES to place CAN module in reset

// here's one example of setting up the bit timing
// set prescaler to divide by 8 (value=7)
// with 16MHz crystal, after /8, tqP0ns
CBTR0=0x07;
// set SAMP=0, TSEG2=3 for 4tq and TSEG1=2 for 3tq
// with sync segment this makes 8 tq per bit with sample point at 5/8c%
CBTR1=0x32; // for a CAN Baud of 250kbps at 16Mhz crystal
//eg. 16Mhz/8/8%0k

// here's another example of setting up the bit timing
// set prescaler to divide by 8 (value=7) with Synch jump width=4 tq (0xC0)
// with 16MHz crystal, after /8, tqP0ns
//CBTR0=0xC7;
// set SAMP=0, TSEG2=4 for 5tq and TSEG1=9 for 10tq
// with sync segment this makes 16 tq per bit with sample point at 11/16i%
//CBTR1=0x49; // for a CAN Baud of 125kbps at 16Mhz crystal
// 16Mhz/8/165K

// CTCR will default to 0
// CIDAC will default to 0 which sets it to "Two 32 bit acceptance filters"
CIDMR0=0xFF; // set filters to receive all messages regardless of acceptance
CIDMR1=0xFF; // filters
CIDMR2=0xFF;
CIDMR3=0xFF;

CMCR0 &=~1; // clear SFTRES to take CAN out of reset
while (!(CMCR0 & 0x10)); // synch to CAN bus
}

----- Original Message -----
From: bdcps2002
To:
Sent: Tuesday, September 10, 2002 2:58 PM
Subject: [68HC12] 9S12DP256 CAN Initialization Hi everybody,
I am using MC9S12DP256 on TechnologicalArts board, which has 2 CAN
ports. Even though CAN works in Loopback mode, I couldn't get them to
talk to each other.
When initializing, do I have to do anything other than:

// Enable MSCAN module.???? Anything else to seperate it from
// being used as general I/0
CAN0CTL1 |= 0x80;
// set SFTRES to place CAN module in reset (initialization)
CAN0CTL0 |= 1;
// clear Listen Only Mode
CAN0CTL1 &= 0xEF;
// Enable timers
CAN0CTL0 |= 0x08;

// Enable Loopback
//CAN0CTL1 |= 0x20;

CAN0BTR0=0xC1;
CAN0BTR1 = 0x4C;
CAN0IDMR0 = 0xFF;

CAN0IDMR1 = 0xFF;
CAN0IDMR2 = 0xFF;
CAN0IDMR3 = 0xFF;

CAN0RIER = 0;
CAN0TIER = 0;

CAN0CTL0 &=~1;
while (!(CAN0CTL0 & 0x10));

Thanks a lot for any insights.
Dzung.
--------------------
">http://docs.yahoo.com/info/terms/


Reply by bdcps2002 ●September 10, 20022002-09-10
--- In 68HC12@y..., "Steve Letkeman" <zanthic@z...> wrote:
> This should help you out a bit
>
> Steve
>
> Zanthic Technologies Inc. is located at www.zanthic.com
> Your Controller Area Networking Experts!
> Embedded micro-controllers and CAN interface devices sold here

Hi Steve,
Thanks for your response! I still haven't been able to figure out
what is wrong. As soon as it tries to send out a CAN message, it goes
to bus-off state right away. I used the scope to watch, and there was
no data at all on CAN_H, CAN_L.
Do you have any ideas?
Thanks a lot.
Dzung. >
> // This file may be freely distributed as long as this header
remains
> // intact in order to encourage you to visit our web site at
www.zanthic.com
>
> // This simple program was written as a quick and easy
> // example of initializing and testing the msCAN port
> // on an HC912BC32 processor.
> // This program was written as a single file for
> // simplicity and only some of the registers are included.
> // Written by Steve Letkeman Feb 2001
>
> // compiled using the ICC12 compiler from imagecraft
(www.imagecraft.com)
> // and tested on the CME-12BC32 development board from Axiom
(www.axman.com)
>
> #include <hc12.h>
> //#include "vectors.c"
> void CANInit(void);
>
> #define _CAN_BASE 0x0100 // CAN Base Address
> #define _CP(off) *(unsigned char volatile *)(_CAN_BASE + off)
>
> #define CMCR0 _CP(0) // Control Register 0
> #define CMCR1 _CP(1) // Control Register 1
> #define CBTR0 _CP(2) // Bus Timing Register 0
> #define CBTR1 _CP(3) // Bus Timing Register 1
> #define CRFLG _CP(4) // Receiver Flag Register
> #define CRIER _CP(5) // Receiver Interrupt Enable Register
> #define CTFLG _CP(6) // Transmitter Flag Register
> #define CTCR _CP(7) // Transmitter Control Register
> #define CIDAC _CP(8) // Identifier Acceptance Control Register
> #define CRXERR _CP(0x0E) // Receive Error Counter
> #define CTXERR _CP(0x0F) // Transmitter Error Counter
> #define CIDAR0 _CP(0x10) // Acceptance Register 0
> #define CIDAR1 _CP(0x11) // Acceptance Register 1
> #define CIDAR2 _CP(0x12) // Acceptance Register 2
> #define CIDAR3 _CP(0x13) // Acceptance Register 3
> #define CIDMR0 _CP(0x14) // Identifier Mask Register 0
> #define CIDMR1 _CP(0x15) // Identifier Mask Register 1
> #define CIDMR2 _CP(0x16) // Identifier Mask Register 2
> #define CIDMR3 _CP(0x17) // Identifier Mask Register 3
> #define CIDAR4 _CP(0x18) // Acceptance Register 4
> #define CIDAR5 _CP(0x19) // Acceptance Register 5
> #define CIDAR6 _CP(0x1A) // Acceptance Register 6
> #define CIDAR7 _CP(0x1B) // Acceptance Register 7
> #define CIDMR4 _CP(0x1C) // Identifier Mask Register 4
> #define CIDMR5 _CP(0x1D) // Identifier Mask Register 5
> #define CIDMR6 _CP(0x1E) // Identifier Mask Register 6
> #define CIDMR7 _CP(0x1F) // Identifier Mask Register 7
> #define PCTLCAN _CP(0x3D) // Control Register
> #define PORTCAN _CP(0x3E) // Data Register
> #define DDRCAN _CP(0x3F) // Data Direction Register
> // from page 129 68HC912BC32.pdf
>
> #define RXIDR0 _CP(0x40) // first byte of ID for the receive buffer
> #define RXIDR1 _CP(0x41) // 2nd byte of ID for the receive buffer
> #define RXIDR2 _CP(0x42) // 3rd byte of ID for the receive buffer
> #define RXIDR3 _CP(0x43) // 4th byte of ID for the receive buffer
> #define RXDSR0 _CP(0x44) // first byte of data for the receive
buffer
> #define RXDLR _CP(0x4C) // Data Length (number of bytes received)
>
> // create defines for the first transmit message object. The
> // other 2 are not defined
> #define TX0IDR0 _CP(0x50) // first byte of ID for the transmit
buffer 0
> #define TX0IDR1 _CP(0x51) // second byte of ID for the transmit
buffer 0
> #define TX0IDR2 _CP(0x52) // third byte of ID for the transmit
buffer 0
> #define TX0IDR3 _CP(0x53) // fourth byte of ID for the transmit
buffer 0
> #define TX0DSR0 _CP(0x54) // first byte of data
> #define TX0DSR1 _CP(0x55) // second byte of data...3-8 are left to
you
> #define TX0DLR _CP(0x5C) // Data Length Register
> #define TX0PRI _CP(0x5D) // Priority
>
> #define TBPR _CP(0xBD) // Transmit Buffer Priority Registers
>
> void main()
> {
> unsigned char x;
> setbaud(BAUD9600); // initialize serial port for text
output
> printf("CAN Test Program\n");
>
> COPCTL=0; // turn off watchdog
> CANInit(); // initial CAN port
>
> printf("transmitting a message\n");
> TX0IDR0=0xAA; // 29 bit ID with 1010 pattern for all 29 bits
> TX0IDR1=0xAA; // 29 bit is defined by setting bit 3
> TX0IDR2=0xAA;
> TX0IDR3=0xAA;
> TX0DSR0=0x55; // first byte of data
> TX0DSR1=0x66; // second byte of data
> TX0DLR=0x02; // set to send 2 bytes of data
>
> while(!(CTFLG & 1)); //wait until Tx buffer is available
> CTFLG = 1; //transmit
> printf("Message transmitted\n");
> printf("Transmit error counter =%d\n",CTXERR); // check for errors
>
> while(1)
> {
> printf("\nwaiting for incoming CAN message\n");
> while(!(CRFLG & 1)); //wait for CAN incoming CAN message
> printf("Received a message!\n");
> printf("ID Registers=%X-%X-%X-%X\n",RXIDR0,RXIDR1,RXIDR2,RXIDR3);
> if (RXIDR1 & 8) printf("This was a 29 bit message");
> else printf("This was an 11 bit message");
> printf(" with %d bytes of data\n",RXDLR & 0x0F);
> printf("Data=");
> for (x=0;x<(RXDLR&0x0F);x++) // loop through data
> printf("%X ",RXDSR0+x);
> printf("\n");
>
> CRFLG |=1; // clear rec flag
>
> // transmit the initial message again
> while(!(CTFLG & 1)); //wait until Tx buffer is available
> CTFLG=1;
> }
> }
>
> void CANInit(void)
> {
> // the following two lines only apply to the Axiom HC12 board
> DDRCAN |=4; // turn on bit 2 which is connected to pin 8 of 82C250
> PORTCAN &=~4; // clear bit to enable
> CMCR0 |=1; // set SFTRES to place CAN module in reset
>
> // here's one example of setting up the bit timing
> // set prescaler to divide by 8 (value=7)
> // with 16MHz crystal, after /8, tqP0ns
> CBTR0=0x07;
> // set SAMP=0, TSEG2=3 for 4tq and TSEG1=2 for 3tq
> // with sync segment this makes 8 tq per bit with sample point at
5/8c%
> CBTR1=0x32; // for a CAN Baud of 250kbps at 16Mhz
crystal
> //eg. 16Mhz/8/8%0k
>
> // here's another example of setting up the bit timing
> // set prescaler to divide by 8 (value=7) with Synch jump width=4
tq (0xC0)
> // with 16MHz crystal, after /8, tqP0ns
> //CBTR0=0xC7;
> // set SAMP=0, TSEG2=4 for 5tq and TSEG1=9 for 10tq
> // with sync segment this makes 16 tq per bit with sample point at
11/16i%
> //CBTR1=0x49; // for a CAN Baud of 125kbps at 16Mhz
crystal
> // 16Mhz/8/165K
>
> // CTCR will default to 0
> // CIDAC will default to 0 which sets it to "Two 32 bit acceptance
filters"
> CIDMR0=0xFF; // set filters to receive all messages regardless of
acceptance
> CIDMR1=0xFF; // filters
> CIDMR2=0xFF;
> CIDMR3=0xFF;
>
> CMCR0 &=~1; // clear SFTRES to take CAN out of reset
> while (!(CMCR0 & 0x10)); // synch to CAN bus
> } >
>
> ----- Original Message -----
> From: bdcps2002
> To: 68HC12@y...
> Sent: Tuesday, September 10, 2002 2:58 PM
> Subject: [68HC12] 9S12DP256 CAN Initialization > Hi everybody,
> I am using MC9S12DP256 on TechnologicalArts board, which has 2
CAN
> ports. Even though CAN works in Loopback mode, I couldn't get
them to
> talk to each other.
> When initializing, do I have to do anything other than:
>
> // Enable MSCAN module.???? Anything else to seperate it from
> // being used as general I/0
> CAN0CTL1 |= 0x80;
> // set SFTRES to place CAN module in reset (initialization)
> CAN0CTL0 |= 1;
> // clear Listen Only Mode
> CAN0CTL1 &= 0xEF;
> // Enable timers
> CAN0CTL0 |= 0x08;
>
> // Enable Loopback
> //CAN0CTL1 |= 0x20;
>
> CAN0BTR0=0xC1;
> CAN0BTR1 = 0x4C;
> CAN0IDMR0 = 0xFF;
>
> CAN0IDMR1 = 0xFF;
> CAN0IDMR2 = 0xFF;
> CAN0IDMR3 = 0xFF;
>
> CAN0RIER = 0;
> CAN0TIER = 0;
>
> CAN0CTL0 &=~1;
> while (!(CAN0CTL0 & 0x10));
>
> Thanks a lot for any insights.
> Dzung. >
> -------------------- >
> ">http://docs.yahoo.com/info/terms/




Reply by Steve Letkeman ●September 10, 20022002-09-10
What kind of physical layer to you have set up, CAN bus transceiver,
termination resistors etc? Is the Tx pin going low or sending continuous
pulses?

Steve

Zanthic Technologies Inc. is located at www.zanthic.com
Your Controller Area Networking Experts!
Embedded micro-controllers and CAN interface devices sold here

----- Original Message -----
From: bdcps2002
To:
Sent: Tuesday, September 10, 2002 3:56 PM
Subject: [68HC12] Re: 9S12DP256 CAN Initialization --- In 68HC12@y..., "Steve Letkeman" <zanthic@z...> wrote:
> This should help you out a bit
>
> Steve
>
> Zanthic Technologies Inc. is located at www.zanthic.com
> Your Controller Area Networking Experts!
> Embedded micro-controllers and CAN interface devices sold here

Hi Steve,
Thanks for your response! I still haven't been able to figure out
what is wrong. As soon as it tries to send out a CAN message, it goes
to bus-off state right away. I used the scope to watch, and there was
no data at all on CAN_H, CAN_L.
Do you have any ideas?
Thanks a lot.
Dzung. >
> // This file may be freely distributed as long as this header
remains
> // intact in order to encourage you to visit our web site at
www.zanthic.com
>
> // This simple program was written as a quick and easy
> // example of initializing and testing the msCAN port
> // on an HC912BC32 processor.
> // This program was written as a single file for
> // simplicity and only some of the registers are included.
> // Written by Steve Letkeman Feb 2001
>
> // compiled using the ICC12 compiler from imagecraft
(www.imagecraft.com)
> // and tested on the CME-12BC32 development board from Axiom
(www.axman.com)
>
> #include <hc12.h>
> //#include "vectors.c"
> void CANInit(void);
>
> #define _CAN_BASE 0x0100 // CAN Base Address
> #define _CP(off) *(unsigned char volatile *)(_CAN_BASE + off)
>
> #define CMCR0 _CP(0) // Control Register 0
> #define CMCR1 _CP(1) // Control Register 1
> #define CBTR0 _CP(2) // Bus Timing Register 0
> #define CBTR1 _CP(3) // Bus Timing Register 1
> #define CRFLG _CP(4) // Receiver Flag Register
> #define CRIER _CP(5) // Receiver Interrupt Enable Register
> #define CTFLG _CP(6) // Transmitter Flag Register
> #define CTCR _CP(7) // Transmitter Control Register
> #define CIDAC _CP(8) // Identifier Acceptance Control Register
> #define CRXERR _CP(0x0E) // Receive Error Counter
> #define CTXERR _CP(0x0F) // Transmitter Error Counter
> #define CIDAR0 _CP(0x10) // Acceptance Register 0
> #define CIDAR1 _CP(0x11) // Acceptance Register 1
> #define CIDAR2 _CP(0x12) // Acceptance Register 2
> #define CIDAR3 _CP(0x13) // Acceptance Register 3
> #define CIDMR0 _CP(0x14) // Identifier Mask Register 0
> #define CIDMR1 _CP(0x15) // Identifier Mask Register 1
> #define CIDMR2 _CP(0x16) // Identifier Mask Register 2
> #define CIDMR3 _CP(0x17) // Identifier Mask Register 3
> #define CIDAR4 _CP(0x18) // Acceptance Register 4
> #define CIDAR5 _CP(0x19) // Acceptance Register 5
> #define CIDAR6 _CP(0x1A) // Acceptance Register 6
> #define CIDAR7 _CP(0x1B) // Acceptance Register 7
> #define CIDMR4 _CP(0x1C) // Identifier Mask Register 4
> #define CIDMR5 _CP(0x1D) // Identifier Mask Register 5
> #define CIDMR6 _CP(0x1E) // Identifier Mask Register 6
> #define CIDMR7 _CP(0x1F) // Identifier Mask Register 7
> #define PCTLCAN _CP(0x3D) // Control Register
> #define PORTCAN _CP(0x3E) // Data Register
> #define DDRCAN _CP(0x3F) // Data Direction Register
> // from page 129 68HC912BC32.pdf
>
> #define RXIDR0 _CP(0x40) // first byte of ID for the receive buffer
> #define RXIDR1 _CP(0x41) // 2nd byte of ID for the receive buffer
> #define RXIDR2 _CP(0x42) // 3rd byte of ID for the receive buffer
> #define RXIDR3 _CP(0x43) // 4th byte of ID for the receive buffer
> #define RXDSR0 _CP(0x44) // first byte of data for the receive
buffer
> #define RXDLR _CP(0x4C) // Data Length (number of bytes received)
>
> // create defines for the first transmit message object. The
> // other 2 are not defined
> #define TX0IDR0 _CP(0x50) // first byte of ID for the transmit
buffer 0
> #define TX0IDR1 _CP(0x51) // second byte of ID for the transmit
buffer 0
> #define TX0IDR2 _CP(0x52) // third byte of ID for the transmit
buffer 0
> #define TX0IDR3 _CP(0x53) // fourth byte of ID for the transmit
buffer 0
> #define TX0DSR0 _CP(0x54) // first byte of data
> #define TX0DSR1 _CP(0x55) // second byte of data...3-8 are left to
you
> #define TX0DLR _CP(0x5C) // Data Length Register
> #define TX0PRI _CP(0x5D) // Priority
>
> #define TBPR _CP(0xBD) // Transmit Buffer Priority Registers
>
> void main()
> {
> unsigned char x;
> setbaud(BAUD9600); // initialize serial port for text
output
> printf("CAN Test Program\n");
>
> COPCTL=0; // turn off watchdog
> CANInit(); // initial CAN port
>
> printf("transmitting a message\n");
> TX0IDR0=0xAA; // 29 bit ID with 1010 pattern for all 29 bits
> TX0IDR1=0xAA; // 29 bit is defined by setting bit 3
> TX0IDR2=0xAA;
> TX0IDR3=0xAA;
> TX0DSR0=0x55; // first byte of data
> TX0DSR1=0x66; // second byte of data
> TX0DLR=0x02; // set to send 2 bytes of data
>
> while(!(CTFLG & 1)); //wait until Tx buffer is available
> CTFLG = 1; //transmit
> printf("Message transmitted\n");
> printf("Transmit error counter =%d\n",CTXERR); // check for errors
>
> while(1)
> {
> printf("\nwaiting for incoming CAN message\n");
> while(!(CRFLG & 1)); //wait for CAN incoming CAN message
> printf("Received a message!\n");
> printf("ID Registers=%X-%X-%X-%X\n",RXIDR0,RXIDR1,RXIDR2,RXIDR3);
> if (RXIDR1 & 8) printf("This was a 29 bit message");
> else printf("This was an 11 bit message");
> printf(" with %d bytes of data\n",RXDLR & 0x0F);
> printf("Data=");
> for (x=0;x<(RXDLR&0x0F);x++) // loop through data
> printf("%X ",RXDSR0+x);
> printf("\n");
>
> CRFLG |=1; // clear rec flag
>
> // transmit the initial message again
> while(!(CTFLG & 1)); //wait until Tx buffer is available
> CTFLG=1;
> }
> }
>
> void CANInit(void)
> {
> // the following two lines only apply to the Axiom HC12 board
> DDRCAN |=4; // turn on bit 2 which is connected to pin 8 of 82C250
> PORTCAN &=~4; // clear bit to enable
> CMCR0 |=1; // set SFTRES to place CAN module in reset
>
> // here's one example of setting up the bit timing
> // set prescaler to divide by 8 (value=7)
> // with 16MHz crystal, after /8, tqP0ns
> CBTR0=0x07;
> // set SAMP=0, TSEG2=3 for 4tq and TSEG1=2 for 3tq
> // with sync segment this makes 8 tq per bit with sample point at
5/8c%
> CBTR1=0x32; // for a CAN Baud of 250kbps at 16Mhz
crystal
> //eg. 16Mhz/8/8%0k
>
> // here's another example of setting up the bit timing
> // set prescaler to divide by 8 (value=7) with Synch jump width=4
tq (0xC0)
> // with 16MHz crystal, after /8, tqP0ns
> //CBTR0=0xC7;
> // set SAMP=0, TSEG2=4 for 5tq and TSEG1=9 for 10tq
> // with sync segment this makes 16 tq per bit with sample point at
11/16i%
> //CBTR1=0x49; // for a CAN Baud of 125kbps at 16Mhz
crystal
> // 16Mhz/8/165K
>
> // CTCR will default to 0
> // CIDAC will default to 0 which sets it to "Two 32 bit acceptance
filters"
> CIDMR0=0xFF; // set filters to receive all messages regardless of
acceptance
> CIDMR1=0xFF; // filters
> CIDMR2=0xFF;
> CIDMR3=0xFF;
>
> CMCR0 &=~1; // clear SFTRES to take CAN out of reset
> while (!(CMCR0 & 0x10)); // synch to CAN bus
> } >
>
> ----- Original Message -----
> From: bdcps2002
> To: 68HC12@y...
> Sent: Tuesday, September 10, 2002 2:58 PM
> Subject: [68HC12] 9S12DP256 CAN Initialization > Hi everybody,
> I am using MC9S12DP256 on TechnologicalArts board, which has 2
CAN
> ports. Even though CAN works in Loopback mode, I couldn't get
them to
> talk to each other.
> When initializing, do I have to do anything other than:
>
> // Enable MSCAN module.???? Anything else to seperate it from
> // being used as general I/0
> CAN0CTL1 |= 0x80;
> // set SFTRES to place CAN module in reset (initialization)
> CAN0CTL0 |= 1;
> // clear Listen Only Mode
> CAN0CTL1 &= 0xEF;
> // Enable timers
> CAN0CTL0 |= 0x08;
>
> // Enable Loopback
> //CAN0CTL1 |= 0x20;
>
> CAN0BTR0=0xC1;
> CAN0BTR1 = 0x4C;
> CAN0IDMR0 = 0xFF;
>
> CAN0IDMR1 = 0xFF;
> CAN0IDMR2 = 0xFF;
> CAN0IDMR3 = 0xFF;
>
> CAN0RIER = 0;
> CAN0TIER = 0;
>
> CAN0CTL0 &=~1;
> while (!(CAN0CTL0 & 0x10));
>
> Thanks a lot for any insights.
> Dzung. >
> -------------------- >
> ">http://docs.yahoo.com/info/terms/
--------------------
">http://docs.yahoo.com/info/terms/


Reply by bdcps2002 ●September 10, 20022002-09-10
--- In 68HC12@y..., "Steve Letkeman" <zanthic@z...> wrote:
> What kind of physical layer to you have set up, CAN bus
transceiver,
> termination resistors etc? Is the Tx pin going low or sending
continuous
> pulses?

The evaluation board
( http://www.technologicalarts.com/myfiles/AD9S12DP256.html ) has 2
CAN ports, each has a jumper to configure 120ohm termination
register at each end. They both use 82250 transceiver. I used 2 hand-
made wires to connect CAN_H to CAN_H, and CAN_L to CAN_L.
It seems to me that data couldn't even get from CPU to the
transceivers (I monitored the line from hc12 to 82250. It stayed
idle (5V) all the time).
What do you have in mind?
Again, thanks for your help.
Dzung.

Reply by Steve Letkeman ●September 10, 20022002-09-10
You will have to look at the following:
1) Is your TouCAN module mapped to the correct part of memory. Can
you single step through the setup and see the registers being changed
as expected?
2) Are there any jumpers that connect the TX pins to the transceivers?
3) Can you write to the TX pin like an I/O pin and have it change as
expected or might there be a shorted trace to VCC? (shot in the dark!)

Did they supply any sort of test program with the board?

Steve

Zanthic Technologies Inc. is located at www.zanthic.com
Your Controller Area Networking Experts!
Embedded micro-controllers and CAN interface devices sold here

----- Original Message -----
From: bdcps2002
To:
Sent: Tuesday, September 10, 2002 5:38 PM
Subject: [68HC12] Re: 9S12DP256 CAN Initialization --- In 68HC12@y..., "Steve Letkeman" <zanthic@z...> wrote:
> What kind of physical layer to you have set up, CAN bus
transceiver,
> termination resistors etc? Is the Tx pin going low or sending
continuous
> pulses?

The evaluation board
( http://www.technologicalarts.com/myfiles/AD9S12DP256.html ) has 2
CAN ports, each has a jumper to configure 120ohm termination
register at each end. They both use 82250 transceiver. I used 2 hand-
made wires to connect CAN_H to CAN_H, and CAN_L to CAN_L.
It seems to me that data couldn't even get from CPU to the
transceivers (I monitored the line from hc12 to 82250. It stayed
idle (5V) all the time).
What do you have in mind?
Again, thanks for your help.
Dzung.
--------------------
">http://docs.yahoo.com/info/terms/

Reply by kp_venu ●September 11, 20022002-09-11
Hi Dzung,
From your initialization code I can see that you are clearing
CAN0RIER and CAN0TIER, but these registers are not suppose to write
in initialization mode.(refer S12MSCANUG page.76).
I don't know this solve your problem.
I use following initialization code for 500kbps.
far void MSCANInit(void) // MSCAN module initialization
{
CAN0CTL0 |= 0x01; // place MSCAN12 in soft reset mode

CAN0CTL1 = 0x80; // MSCAN12 module enabled

CAN0BTR0 = 0x40; // Baud rate = 500Kbs,
CAN0BTR1 = 0x14; // SAMP = 0; one sample per bit

CAN0IDAC = 0x17; // four 16-bit Acceptance Filters
CAN0IDMR0 = 0xFFFF; // mask register value 0
CAN0IDMR2 = 0xFFFF; // mask register value 2
CAN0IDMR4 = 0xFFFF; // mask register value 4
CAN0IDMR6 = 0xFFFF; // mask register value 6

// FilterConfig(); // Acceptance Filter configuartion for ECU
// located in ECU
Configuration file
CAN0CTL0 &= ~0x01; // take MSCAN12 out of soft reset

CAN0RFLG = MASK_8; // Clear all CAN error flags
CAN0RIER = OVRIE | RXFIE; // Enable interrupts for Error and
receive flags
while(!(CAN0CTL0 & SYNCH)){}; //wait for synchronization with
CAN bus
}
Best Regards,
Venu

--- In 68HC12@y..., "bdcps2002" <bdcps2002@y...> wrote:
> Hi everybody,
> I am using MC9S12DP256 on TechnologicalArts board, which has 2 CAN
> ports. Even though CAN works in Loopback mode, I couldn't get them
to
> talk to each other.
> When initializing, do I have to do anything other than:
>
> // Enable MSCAN module.???? Anything else to seperate it from
> // being used as general I/0
> CAN0CTL1 |= 0x80;
> // set SFTRES to place CAN module in reset (initialization)
> CAN0CTL0 |= 1;
> // clear Listen Only Mode
> CAN0CTL1 &= 0xEF;
> // Enable timers
> CAN0CTL0 |= 0x08;
>
> // Enable Loopback
> //CAN0CTL1 |= 0x20;
>
> CAN0BTR0=0xC1;
> CAN0BTR1 = 0x4C;
> CAN0IDMR0 = 0xFF;
>
> CAN0IDMR1 = 0xFF;
> CAN0IDMR2 = 0xFF;
> CAN0IDMR3 = 0xFF;
>
> CAN0RIER = 0;
> CAN0TIER = 0;
>
> CAN0CTL0 &=~1;
> while (!(CAN0CTL0 & 0x10));
>
> Thanks a lot for any insights.
> Dzung.
Reply by bdcps2002 ●September 11, 20022002-09-11
Hi Venu,
I disabled CANORIER and CANOTIER, but the problem is still there. Are
you using exact board that I am using (Adapt9S12DP256 from
Technological Arts (www.technologicalarts.com) with 2 CAN port
populated). If so, do you have a small program to test CAN ports?
Thanks a lot,
Dzung.

--- In 68HC12@y..., "kp_venu" <kp_venu@y...> wrote:
> Hi Dzung,
> From your initialization code I can see that you are clearing
> CAN0RIER and CAN0TIER, but these registers are not suppose to write
> in initialization mode.(refer S12MSCANUG page.76).
> I don't know this solve your problem.
> I use following initialization code for 500kbps.
> far void MSCANInit(void) // MSCAN module initialization
> {
> CAN0CTL0 |= 0x01; // place MSCAN12 in soft reset mode
>
> CAN0CTL1 = 0x80; // MSCAN12 module enabled
>
> CAN0BTR0 = 0x40; // Baud rate = 500Kbs,
> CAN0BTR1 = 0x14; // SAMP = 0; one sample per bit
>
> CAN0IDAC = 0x17; // four 16-bit Acceptance Filters
> CAN0IDMR0 = 0xFFFF; // mask register value 0
> CAN0IDMR2 = 0xFFFF; // mask register value 2
> CAN0IDMR4 = 0xFFFF; // mask register value 4
> CAN0IDMR6 = 0xFFFF; // mask register value 6
>
> // FilterConfig(); // Acceptance Filter configuartion for ECU
> // located in ECU
> Configuration file
> CAN0CTL0 &= ~0x01; // take MSCAN12 out of soft reset
>
> CAN0RFLG = MASK_8; // Clear all CAN error flags
> CAN0RIER = OVRIE | RXFIE; // Enable interrupts for Error and
> receive flags
> while(!(CAN0CTL0 & SYNCH)){}; //wait for synchronization with
> CAN bus
> }
> Best Regards,
> Venu
>
> --- In 68HC12@y..., "bdcps2002" <bdcps2002@y...> wrote:
> > Hi everybody,
> > I am using MC9S12DP256 on TechnologicalArts board, which has 2
CAN
> > ports. Even though CAN works in Loopback mode, I couldn't get
them
> to
> > talk to each other.
> > When initializing, do I have to do anything other than:
> >
> > // Enable MSCAN module.???? Anything else to seperate it from
> > // being used as general I/0
> > CAN0CTL1 |= 0x80;
> > // set SFTRES to place CAN module in reset (initialization)
> > CAN0CTL0 |= 1;
> > // clear Listen Only Mode
> > CAN0CTL1 &= 0xEF;
> > // Enable timers
> > CAN0CTL0 |= 0x08;
> >
> > // Enable Loopback
> > //CAN0CTL1 |= 0x20;
> >
> > CAN0BTR0=0xC1;
> > CAN0BTR1 = 0x4C;
> > CAN0IDMR0 = 0xFF;
> >
> > CAN0IDMR1 = 0xFF;
> > CAN0IDMR2 = 0xFF;
> > CAN0IDMR3 = 0xFF;
> >
> > CAN0RIER = 0;
> > CAN0TIER = 0;
> >
> > CAN0CTL0 &=~1;
> > while (!(CAN0CTL0 & 0x10));
> >
> > Thanks a lot for any insights.
> > Dzung.
Reply by kp_venu ●September 11, 20022002-09-11
No. We have our own hardware design with DP256.
Venu

--- In 68HC12@y..., "bdcps2002" <bdcps2002@y...> wrote:
> Hi Venu,
> I disabled CANORIER and CANOTIER, but the problem is still there.
Are
> you using exact board that I am using (Adapt9S12DP256 from
> Technological Arts (www.technologicalarts.com) with 2 CAN port
> populated). If so, do you have a small program to test CAN ports?
> Thanks a lot,
> Dzung.
>
> --- In 68HC12@y..., "kp_venu" <kp_venu@y...> wrote:
> > Hi Dzung,
> > From your initialization code I can see that you are clearing
> > CAN0RIER and CAN0TIER, but these registers are not suppose to
write
> > in initialization mode.(refer S12MSCANUG page.76).
> > I don't know this solve your problem.
> > I use following initialization code for 500kbps.
> > far void MSCANInit(void) // MSCAN module initialization
> > {
> > CAN0CTL0 |= 0x01; // place MSCAN12 in soft reset mode
> >
> > CAN0CTL1 = 0x80; // MSCAN12 module enabled
> >
> > CAN0BTR0 = 0x40; // Baud rate = 500Kbs,
> > CAN0BTR1 = 0x14; // SAMP = 0; one sample per bit
> >
> > CAN0IDAC = 0x17; // four 16-bit Acceptance Filters
> > CAN0IDMR0 = 0xFFFF; // mask register value 0
> > CAN0IDMR2 = 0xFFFF; // mask register value 2
> > CAN0IDMR4 = 0xFFFF; // mask register value 4
> > CAN0IDMR6 = 0xFFFF; // mask register value 6
> >
> > // FilterConfig(); // Acceptance Filter configuartion for ECU
> > // located in ECU
> > Configuration file
> > CAN0CTL0 &= ~0x01; // take MSCAN12 out of soft reset
> >
> > CAN0RFLG = MASK_8; // Clear all CAN error flags
> > CAN0RIER = OVRIE | RXFIE; // Enable interrupts for Error and
> > receive flags
> > while(!(CAN0CTL0 & SYNCH)){}; //wait for synchronization with
> > CAN bus
> > }
> > Best Regards,
> > Venu
> >
> > --- In 68HC12@y..., "bdcps2002" <bdcps2002@y...> wrote:
> > > Hi everybody,
> > > I am using MC9S12DP256 on TechnologicalArts board, which has 2
> CAN
> > > ports. Even though CAN works in Loopback mode, I couldn't get
> them
> > to
> > > talk to each other.
> > > When initializing, do I have to do anything other than:
> > >
> > > // Enable MSCAN module.???? Anything else to seperate it from
> > > // being used as general I/0
> > > CAN0CTL1 |= 0x80;
> > > // set SFTRES to place CAN module in reset (initialization)
> > > CAN0CTL0 |= 1;
> > > // clear Listen Only Mode
> > > CAN0CTL1 &= 0xEF;
> > > // Enable timers
> > > CAN0CTL0 |= 0x08;
> > >
> > > // Enable Loopback
> > > //CAN0CTL1 |= 0x20;
> > >
> > > CAN0BTR0=0xC1;
> > > CAN0BTR1 = 0x4C;
> > > CAN0IDMR0 = 0xFF;
> > >
> > > CAN0IDMR1 = 0xFF;
> > > CAN0IDMR2 = 0xFF;
> > > CAN0IDMR3 = 0xFF;
> > >
> > > CAN0RIER = 0;
> > > CAN0TIER = 0;
> > >
> > > CAN0CTL0 &=~1;
> > > while (!(CAN0CTL0 & 0x10));
> > >
> > > Thanks a lot for any insights.
> > > Dzung.




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