max MIPS of at91sam7s64

The embedded flash requires 1 wait state when running above 30 MHz.

--- In AT91SAM@AT91..., nader chinichian <naderus2000@...> wrote:
>
> hi,
>   i read in the datasheet that s64 with up to 55 MHZ & the MIPS is
0.9 mips/mhz so it 
>   can up to 49.5 MIPS.
>   but in the a app note i read the max speed for reading the flash
is 33 ns give the max 27 mips.
>   so  i want to s64 can work with 49.5 mips or
not?
	

Hi,

The MIP's number (0.9MIPS/MHz) is based on the DMIPs code and
realistically only should be used as a yardstick measure. It assumes
0-wait state memory and ARM code.

Depending on your code using Thumb code may reduce the MIP's. Thumb
instructions while yielding smaller code size also reduces the
"capability" of each instruction. It may be better to use a mix of ARM
and Thumb.

I agree the best performance will be achieved by profiling your code
and placing frequently called functions in internal SRAM.

Can anyone comment if the the Internal SRAM is TCM or AHB?

Thanks,
Ken

--- In AT91SAM@AT91..., "Andreas Siebel" <im_urlaub@...> wrote:
>
> Hi,
>  
> you can only get the maximum speed in arm mode if you execute from sram.
>  
> As far as I know it is also possible to get the maximum speed if you
> execute from flash if you use thumb instructions. The core reads two
> instructions at one time from the flash and puts them in the pipeline.
> This is possible at the maximum core clock with one wait state when
> doing flash reads.
>  
> -----Ursprgliche Nachricht-----
> Von: AT91SAM@AT91... [mailto:AT91SAM@AT91...] Im Auftrag
> von nader chinichian
> Gesendet: Dienstag, 7. Mz 2006 19:03
> An: AT91SAM@AT91...
> Betreff: [AT91SAM] max MIPS of at91sam7s64
>  
> hi,
> i read in the datasheet that s64 with up to 55 MHZ & the MIPS is 0.9
> mips/mhz so it 
> can up to 49.5 MIPS.
> but in the a app note i read the max speed for reading the flash is 33
> ns give the max 27 mips.
> so  i want to s64 can work with 49.5 mips or not?
>  
>   _____  
> 
> Yahoo! Mail
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Some say that MIPS stands for "Meaningless Indication
of Processor Speed"....

It is just a number that shows how many instructions
the CPU can perform without taking into account what
these instructions are doing.
The exact MIPS depends on:
1) cpu clock - to ignore this factor they use MIPS/MHz
2) how many clocks one instruction takes
3) architecture limits. For example it wouldn't matter
how fast is the cpu if it cannot fetch enough
instructions.
	Now, we are talking about ARM core where the
instructions speed is usally measured in bus clocks
not cpu clocks. Here I can only assume that the
internal bus clock equals to cpu clock and also there
are no extra penalties like betwen S and N type
cycles...
With these assumptions most of the instructions take 1
clock, so you can have peak performance of 1 MIPS/MHz.
Some instructions like STR needs 2 clocks, some like
LDR needs 3 clocks and other like load/store multiple
can take more clocks.
They say 0.9 MIPS/MHz as average I suppouse. 

About the limitations... if run from SRAM, there are
no limitations.
If you run from flash and clock bellow 30MHz - no
limitations. Above 30MHz, 1ws is required and this
affects the MIPS in the following way:
1) for ARM instructions set, MIPS/MHz will get twice
lower. So if you have 27MIPS @ 30MHz, you will get
only 25MIPS @ 55MHz. Odd insn't ?!
2) for Thumb instruction set, due to the pipeline the
speed is reduced for non-sequencial bus cycles only,
so the MIPS probably will get 0.6-0.7 or 30-40MIPS @
55MHz

In fact I see no reasons someone to use ARM
instructions sets, except for assembler written
procedures for heavy math processing stuff. 

Once again, this kind of performance measurement is
kind of useless... I can say that so far I am
impressed from the performance of SAM7S64.

Miro
	--- kendwyer <kendwyer@kend...> wrote:

> Hi,
> 
> The MIP's number (0.9MIPS/MHz) is based on the DMIPs
> code and
> realistically only should be used as a yardstick
> measure. It assumes
> 0-wait state memory and ARM code.
> 
> Depending on your code using Thumb code may reduce
> the MIP's. Thumb
> instructions while yielding smaller code size also
> reduces the
> "capability" of each instruction. It may be better
> to use a mix of ARM
> and Thumb.
> 
> I agree the best performance will be achieved by
> profiling your code
> and placing frequently called functions in internal
> SRAM.
> 
> Can anyone comment if the the Internal SRAM is TCM
> or AHB?
> 
> Thanks,
> Ken
> 
> --- In AT91SAM@AT91..., "Andreas Siebel"
> <im_urlaub@...> wrote:
> >
> > Hi,
> >  
> > you can only get the maximum speed in arm mode if
> you execute from sram.
> >  
> > As far as I know it is also possible to get the
> maximum speed if you
> > execute from flash if you use thumb instructions.
> The core reads two
> > instructions at one time from the flash and puts
> them in the pipeline.
> > This is possible at the maximum core clock with
> one wait state when
> > doing flash reads.
> >  
> > -----Ursprgliche Nachricht-----
> > Von: AT91SAM@AT91...
> [mailto:AT91SAM@AT91...] Im Auftrag
> > von nader chinichian
> > Gesendet: Dienstag, 7. Mz 2006 19:03
> > An: AT91SAM@AT91...
> > Betreff: [AT91SAM] max MIPS of at91sam7s64
> >  
> > hi,
> > i read in the datasheet that s64 with up to 55 MHZ
> & the MIPS is 0.9
> > mips/mhz so it 
> > can up to 49.5 MIPS.
> > but in the a app note i read the max speed for
> reading the flash is 33
> > ns give the max 27 mips.
> > so  i want to s64 can work with 49.5 mips or not?
> >  
> >   _____  
> > 
> > Yahoo! Mail
> > Bring photos to life! New
> >
>
<http://pa.yahoo.com/*http:/us.rd.yahoo.com/evt9174/*http:/photomail.m
> > ail.yahoo.com>  PhotoMail makes sharing a
breeze. 
> > SPONSORED LINKS 
> > 
> > Microcontrollers
> >
>
<http://groups.yahoo.com/gads?t=ms&k=Microcontrollers&w1=Microcontroller
> >
>
s&w2=Cpu+chip&w3=Arms&w4elopment+tool&w5=Microprocessor&c=5&s&.si
> > g=JL1WKF1vUqEgZhFSvLcTwQ>  
> > Cpu
> >
>
<http://groups.yahoo.com/gads?t=ms&k=Cpu+chip&w1=Microcontrollers&w2=Cpu
> >
>
+chip&w3=Arms&w4elopment+tool&w5=Microprocessor&c=5&s&.sig=J2LJ4J
> > ioN5vEM0428aODAg>  chip 
> > Arms
> >
>
<http://groups.yahoo.com/gads?t=ms&k=Arms&w1=Microcontrollers&w2=Cpu+chi
> >
>
p&w3=Arms&w4elopment+tool&w5=Microprocessor&c=5&s&.sig=yPOxLkzDXn
> > 5eqYeA1wMVCQ>  
> > 
> > Development
> >
>
<http://groups.yahoo.com/gads?t=ms&kelopment+tool&w1=Microcontroller
> >
>
s&w2=Cpu+chip&w3=Arms&w4elopment+tool&w5=Microprocessor&c=5&s&.si
> > g=lhbODg5ptVr7u61IFQfZXQ>  tool 
> > Microprocessor
> >
>
<http://groups.yahoo.com/gads?t=ms&k=Microprocessor&w1=Microcontrollers&
> >
>
w2=Cpu+chip&w3=Arms&w4elopment+tool&w5=Microprocessor&c=5&s&.sig>
> CHIRUROYao456Telb69zdA>  
> >  
> >  
> >   _____  
> > 
> > >  Terms of
> Service. 
> >  
> >   _____
> >
> 
> 
> 
> 
> 
>
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