SPI PDC Transfers

I plan to implement SPI DMA Transfers using the AT91SAM7S256 eval
board with an SPI Device, and I'd like some clarification on how the
SPI_PDC pointers access the data while the PDC's enabled.

>From the SPI section in the AT91SAM7S256 user manual (latest), I
notice that both SPI Transmit & Receive registers have 16-bit data
fields (TD & RD), yet the SPI communicates data 8-bits at a time.

Do the SPI_PDC pointers really access data for sending/receiving data
16 bits at a time (meaning 2 SPI transfers for every counter change),
or do the pointers access data 8-bits at a time?

Thanks,

Leighton Start a New Thread

hello,
the data bit lenght depends on the SPI device. the at91sam7s supports
data bit length from 8 to 16 bit. this is the reason why the receive
and transmit register are 16 bit wide. the data length is programmable
via the CS register for each slave individually.
you can use the function AT91F_SPI_CfgCs (from lib_AT91SAM7S256.h) for
configuring the spi interface.

here an example sequence for initializing the spi interface:
AT91F_PIO_CfgPeriph(....);
AT91F_SPI_CfgPMC();
AT91F_SPI_Reset(AT91C_BASE_SPI);
AT91F_SPI_CfgMode(...);
AT91F_SPI_CfgCs(AT91C_BASE_SPI, Slave-nr,...);

the easiest way to send data with the pdc is using the function
AT91F_SPI_SendFrame(...).
receiving works with AT91F_SPI_ReceiveFrame(..).
hope this helps
tom
--- In A..., "Leighton Rowe"
wrote:
>
> I plan to implement SPI DMA Transfers using the AT91SAM7S256 eval
> board with an SPI Device, and I'd like some clarification on how the
> SPI_PDC pointers access the data while the PDC's enabled.
>
> From the SPI section in the AT91SAM7S256 user manual (latest), I
> notice that both SPI Transmit & Receive registers have 16-bit data
> fields (TD & RD), yet the SPI communicates data 8-bits at a time.
>
> Do the SPI_PDC pointers really access data for sending/receiving
data
> 16 bits at a time (meaning 2 SPI transfers for every counter change)
,
> or do the pointers access data 8-bits at a time?
>
> Thanks,
>
> Leighton
> Start a New Thread

Hey Tom,

Thanks for your reply. That will help me alot. I'll also be looking
out for a problem (post #1152 by Foltos) that may occur
transmit/receive PDC transfers occured simultaneously.

thanks,
Leighton Start a New Thread

Hello,

For the SPI_PDC the recive side uses 32 bit transfers per SPI data
transfer (8 to 16 bits of data + SPI channel). On the recive side the
whole SPI recive data register is moved to the buffer ram.

I expect that the transmit PDC would work in a similar way, though I
have not tested this.
Regards Peter Start a New Thread