NVM bit 2 (Boot control) on SAM7X256

I am trying to get to a point where my user interface can issue the
commands to tell the processor to boot from loader (ROM) at next
powerup instead of flash. The problem is that the code runs fine in
single step mode in both ARM and THUMB modes, however ends up in the
pabort_handler if it's run in either ARM or THUMB mode. At this point
it is a mear annoyance, however I would like to know if there is a way
to fix this.

Any Clues? Code Follows.
void SetBoot2Flash(void)
{
long testport;
testport = *AT91C_MC_FSR; // pointer to status reg
if (( testport & 0x00000400) == 0x00000000) // is NVM bit 2 clear?
{
*AT91C_MC_FCR = 0x5A00020B; // set NVM bit 2
}
while ((testport & 0x00000001) == 0x00000000);// wait for command
}

- Jim Start a New Thread

Have you remembered to set the FMCN field of MC_FMR correctly ?

-kjell eirik
On 8/23/06, James wrote:
>
> I am trying to get to a point where my user interface can issue the
> commands to tell the processor to boot from loader (ROM) at next
> powerup instead of flash. The problem is that the code runs fine in
> single step mode in both ARM and THUMB modes, however ends up in the
> pabort_handler if it's run in either ARM or THUMB mode. At this point
> it is a mear annoyance, however I would like to know if there is a way
> to fix this.
>
> Any Clues? Code Follows.
> void SetBoot2Flash(void)
> {
> long testport;
> testport = *AT91C_MC_FSR; // pointer to status reg
> if (( testport & 0x00000400) == 0x00000000) // is NVM bit 2 clear?
> {
> *AT91C_MC_FCR = 0x5A00020B; // set NVM bit 2
> }
> while ((testport & 0x00000001) == 0x00000000);// wait for command
> }
>
> - Jim
> Start a New Thread

With a master clock of 47.9232Mhz a setting of 50 should be 1.04 mS.
The Atmel documentation says 1ms for NVM bits 1.5ms for flash, I'm not writing flash, however, I
am willing to try setting it to 1.5ms for a test.
I set it to a value of 72, (1.502mS) which did not change the condition.

Still puzzled!

-Jim

--- kjell eirik andersen wrote:

> Have you remembered to set the FMCN field of MC_FMR correctly ?
>
> -kjell eirik
> On 8/23/06, James wrote:
> >
> > I am trying to get to a point where my user interface can issue the
> > commands to tell the processor to boot from loader (ROM) at next
> > powerup instead of flash. The problem is that the code runs fine in
> > single step mode in both ARM and THUMB modes, however ends up in the
> > pabort_handler if it's run in either ARM or THUMB mode. At this point
> > it is a mear annoyance, however I would like to know if there is a way
> > to fix this.
> >
> > Any Clues? Code Follows.
> > void SetBoot2Flash(void)
> > {
> > long testport;
> > testport = *AT91C_MC_FSR; // pointer to status reg
> > if (( testport & 0x00000400) == 0x00000000) // is NVM bit 2 clear?
> > {
> > *AT91C_MC_FCR = 0x5A00020B; // set NVM bit 2
> > }
> > while ((testport & 0x00000001) == 0x00000000);// wait for command
> > }
> >
> > - Jim
> >
> >
>

__________________________________________________ Start a New Thread

My suggestion is that the writing of NVM bits is controlled by the flash
controller.
So the code that changes NVM bits cannot be run from flash.
You can singlestep this code, becasue then it is basically injected inte
the CPU by
the debugger, not continously read from flash by the cpu.
The solution is to placxe/copy a small function to RAM as "fastcode" and
run all
flash modifications, including NVM bits from RAM.

--- In A..., James Anderson wrote:
> With a master clock of 47.9232Mhz a setting of 50 should be 1.04 mS.
> The Atmel documentation says 1ms for NVM bits 1.5ms for flash, I'm not
writing flash, however, I
> am willing to try setting it to 1.5ms for a test.
> I set it to a value of 72, (1.502mS) which did not change the
condition.
>
> Still puzzled!
>
> -Jim
>
> --- kjell eirik andersen kjell.e.andersen@... wrote:
>
> > Have you remembered to set the FMCN field of MC_FMR correctly ?
> >
> > -kjell eirik
> >
> >
> > On 8/23/06, James jim_255_2@... wrote:
> > >
> > > I am trying to get to a point where my user interface can issue
the
> > > commands to tell the processor to boot from loader (ROM) at next
> > > powerup instead of flash. The problem is that the code runs fine
in
> > > single step mode in both ARM and THUMB modes, however ends up in
the
> > > pabort_handler if it's run in either ARM or THUMB mode. At this
point
> > > it is a mear annoyance, however I would like to know if there is a
way
> > > to fix this.
> > >
> > > Any Clues? Code Follows.
> > > void SetBoot2Flash(void)
> > > {
> > > long testport;
> > > testport = *AT91C_MC_FSR; // pointer to status reg
> > > if (( testport & 0x00000400) == 0x00000000) // is NVM bit 2 clear?
> > > {
> > > *AT91C_MC_FCR = 0x5A00020B; // set NVM bit 2
> > > }
> > > while ((testport & 0x00000001) == 0x00000000);// wait for command
> > > }
> > >
> > > - Jim
> > >
> > >
> > >
> >
> __________________________________________________ Start a New Thread

This problem has dropped to quite low on my priority list, however I
have compiled the routine in question to load to 'fast_run' section,
have verified that Indeed it IS executing from RAM, however it still
gets a prefetch abort exception upon return to flash. I have even
tryed stretching the routine with nop instructions.

Any other ideas?
--- In A..., "Magnus Lundin" wrote:
>
> My suggestion is that the writing of NVM bits is controlled by the
flash
> controller.
> So the code that changes NVM bits cannot be run from flash.
> You can singlestep this code, becasue then it is basically
injected inte
> the CPU by
> the debugger, not continously read from flash by the cpu.
> The solution is to placxe/copy a small function to RAM
as "fastcode" and
> run all
> flash modifications, including NVM bits from RAM.
>
> --- In A..., James Anderson wrote:
> >
> >
> > With a master clock of 47.9232Mhz a setting of 50 should be 1.04
mS.
> > The Atmel documentation says 1ms for NVM bits 1.5ms for flash,
I'm not
> writing flash, however, I
> > am willing to try setting it to 1.5ms for a test.
> > I set it to a value of 72, (1.502mS) which did not change the
> condition.
> >
> > Still puzzled!
> >
> > -Jim
> >
> > --- kjell eirik andersen kjell.e.andersen@ wrote:
> >
> > > Have you remembered to set the FMCN field of MC_FMR
correctly ?
> > >
> > > -kjell eirik
> > >
> > >
> > > On 8/23/06, James jim_255_2@ wrote:
> > > >
> > > > I am trying to get to a point where my user interface can
issue
> the
> > > > commands to tell the processor to boot from loader (ROM) at
next
> > > > powerup instead of flash. The problem is that the code runs
fine
> in
> > > > single step mode in both ARM and THUMB modes, however ends
up in
> the
> > > > pabort_handler if it's run in either ARM or THUMB mode. At
this
> point
> > > > it is a mear annoyance, however I would like to know if
there is a
> way
> > > > to fix this.
> > > >
> > > > Any Clues? Code Follows.
> > > > void SetBoot2Flash(void)
> > > > {
> > > > long testport;
> > > > testport = *AT91C_MC_FSR; // pointer to status reg
> > > > if (( testport & 0x00000400) == 0x00000000) // is NVM bit 2
clear?
> > > > {
> > > > *AT91C_MC_FCR = 0x5A00020B; // set NVM bit 2
> > > > }
> > > > while ((testport & 0x00000001) == 0x00000000);// wait for
command
> > > > }
> > > >
> > > > - Jim
> > > >
> > > >
> > > >
> > >
> >
> >
> > __________________________________________________
> >
> Start a New Thread

--- In A..., "James" wrote:
>
> This problem has dropped to quite low on my priority list, however I
> have compiled the routine in question to load to 'fast_run' section,
> have verified that Indeed it IS executing from RAM, however it still
> gets a prefetch abort exception upon return to flash. I have even
> tryed stretching the routine with nop instructions.
>
> Any other ideas?
>
Looking at the code, if it still the same that you use, you use the
old value of MC_FSR stored in testport. Try changing the last line to

while ((*AT91C_MC_FSR) & 0x00000001) == 0x00000000);

This will test the actual value of MC_FSR

Regards
Magnus Start a New Thread