Mark McDougall wrote:> Didi wrote: > >> You will not need to match lengths at 133 MHz that much, 10-20 mm won't >> make any difference (just do the math). > As long as the trace lengths from the FPGA to the expansion header are > also taken into account...there is indeed some inevitable variation on the board, like 10 or 15mm between min and max length (i'll have to measure). And i'll take this into account obviously. However I guess that i'll have many problems from other domains before hitting the speed barrier :-) Fortunately, I have a bunch of new 48LC16M16A2 chips and they seem to be widely used. I think that the ACME Fox uses it and I once downloaded the initialisation sequence once... Still, I'm not confident.> Regards,thanks for the hints, yg -- http://ygdes.com / http://yasep.org
How to add some SDRAM to a FPGA board ?
Started by ●January 21, 2009
Reply by ●January 21, 20092009-01-21
Reply by ●January 21, 20092009-01-21
hi, linnix wrote:> There are 10 to 20ns sram in TSOP, and faster if you pay more.I know these, but in the end it's too expensive... even for a proto.> 16 chips in a small PCB is not impractical.it is, for two reasons : price and bus load. I have bought 8ns chips to upgrade the 12ns parts of my ACME boards (see http://news.yasep.org ) and they are only 512KB each. And even 12ns is not cheap. And 16 such chips is not enough capacity. Furthermore, putting 16 chips on the same bus will void their high speed, since the capacitive load on the pins will go beyond reasonable. [in a not so distant youth, i tried to make a high-speed SRAM bank made out of 32KB cache SRAMs from scrapped computers, but the bus loading and the power dissipation cancelled the idea before I started to implement it] And finally, I already have small high-speed SRAMs, the SDRAM is more for "storage" and the access speed is not an issue (<100ns is ok).> Not using PCB at all is impractical.hmmm... I could sacrifice 2 or 3 SDRAM chips, and i have already soldered weird things. So that is still the "easiest" solution before making a custom board. I don't have suitable proto boards either. Broke, weird and lazy is a dangerous combination :-) yg -- http://ygdes.com / http://yasep.org
Reply by ●January 21, 20092009-01-21
CBFalconer wrote:> To evaluate the effects of wire length, consider that 1 foot (1/3 > meter) of wire represents about 1 nS in a vacuum. Probably closer > to 2 nS in your environment. 100 MHz chips are cycling in no more > than 10 nS.Yes but other issues arise. And I've read everywhere that SDRAMs are difficult to use... getting pas initialisation is often described as ... a lot of work.> Also bear in mind that you have to provide the appropriate signals > and addresses to refresh the memory at some interval.that's what bothers me most. I'll check if there is an auto-refresh mode that cuts my efforts. Also : If I scan the buffers sequentially at a known rate (this is for audio samples) then I could arrange the interleaving in such a way that no explicit refresh is needed. I suspect that this method is used in video adapters, since at least one old personal computer (a french 6809-based thing popular around 1984) uses this idea. So I will try to combine both refresh and normal scan...> See the data sheets for this. > The circuitry is a complication, not present in static memory chips.Static RAMs also have their gotchas...> The variation in delays through this > circuitry also need to get absorbed in that 10 nS window.Certainly. Correct data latching is necessary. Damn, I'm almost afraid of what I've got myself into... regards, yg -- http://ygdes.com / http://yasep.org
Reply by ●January 21, 20092009-01-21
On Jan 21, 4:04 pm, whygee <why...@yg.yg> wrote:> hi, > > linnix wrote: > > There are 10 to 20ns sram in TSOP, and faster if you pay more. > > I know these, but in the end it's too expensive... even for a proto. >I read a little bit of your web pages. You are using it for code storage, right? Why can't you use flash?
Reply by ●January 21, 20092009-01-21
In message <4977A18E.C1C7EAD2@yahoo.com>, CBFalconer <cbfalconer@yahoo.com> writes> >Also bear in mind that you have to provide the appropriate signals >and addresses to refresh the memory at some interval. See the data >sheets for this. The circuitry is a complication, not present in >static memory chips. The variation in delays through this >circuitry also need to get absorbed in that 10 nS window.SDRAM requires initialisation during power-up with different signalling patterns to regular RAS-CAS access. The manufacturer's data sheets will give you the gory details -- it's not easy and I'm not sure it can be implemented through software and a simple address/data bus interface from a microcontroller. At least you might have to add a dedicated SDRAM controller chip. An embedded system I worked on added 1-2 Mb of SDRAM to a cell-8051 but there was a lot of dedicated silicon to make the SDRAM run. Static RAM, although more expensive, is going to be easier to add to a test/dev system if you want more memory. It can also be remotely probed (stop the CPU, force the /WR line high then read off the memory contents in dual-port mode. Great for single-step debugging). -- To reply, my gmail address is nojay1 Robert Sneddon
Reply by ●January 21, 20092009-01-21
whygee wrote:>... snip ...> > If I scan the buffers sequentially at a known rate (this is for > audio samples) then I could arrange the interleaving in such a > way that no explicit refresh is needed.If for audio why in the world do you need such high speed chips? -- [mail]: Chuck F (cbfalconer at maineline dot net) [page]: <http://cbfalconer.home.att.net> Try the download section.
Reply by ●January 21, 20092009-01-21
hi, CBFalconer wrote:> whygee wrote: > ... snip ... >> If I scan the buffers sequentially at a known rate (this is for >> audio samples) then I could arrange the interleaving in such a >> way that no explicit refresh is needed. > > If for audio why in the world do you need such high speed chips?well, * I just happen to have a small ribbon (90-ish) of 48LC16M16 that match the speed of my computation core (I stick to 100MHz pipelines) * Whenever I downscale a project, I always end up bitten by the speed demons (ouch) * sound processing, effects, synthesis and whatnot consume so much computational power that, well, I'm not even sure that the A3P1000 will be enough for some of my friends like Satine (http://satinemusic.com/) who use severa laptop on stage but are annoyed by the necessity of using Windows there. * Any headroom or margin is eaten in some way in SW... * In fact I have no idea of what I'll end up doing, so "high speed chips" is questionable with this perspective, if the workload is not yet characterised ;-) * what's wrong with high speed ? :-) * etc. -- http://ygdes.com / http://yasep.org
Reply by ●January 21, 20092009-01-21
hi, linnix wrote:> On Jan 21, 4:04 pm, whygee <why...@yg.yg> wrote: >> linnix wrote: >>> There are 10 to 20ns sram in TSOP, and faster if you pay more. >> I know these, but in the end it's too expensive... even for a proto. > I read a little bit of your web pages. You are using it for code > storage, right? Why can't you use flash?The SDRAM thing just popped up on the surface of my brain since I realised that some DSP/sound applications (that I resurrected) need a lot of volatile storage. Like maybe one minute of sound samples or things like that. The program/code can fit is smaller, faster SRAM. Hope this is clearer now, yg -- http://ygdes.com / http://yasep.org
Reply by ●January 21, 20092009-01-21
Didi wrote:> On Jan 21, 4:38 pm, whygee <why...@yg.yg> wrote: >> Fortunately, the eval boards have rather short traces to the headers >> so impedence will not be a big problem (I hope). > You will not need to match lengths at 133 MHz that much, 10-20 mm > won't make any difference (just do the math). > However, not having a ground plane to reference the signals to may > well become an issue.A thick copper wire will do the trick... I even have some copper sticky tape if needed.> Since this is a one-off thing (I suppose you do not intend to hand- > wire them DDRAMs in mass-production :-) ),Who know if there is ever going to be a production ? :-)> you may be better off if you explore and > cut a piece (literally) from a DDRAM DIMM, some do use DDRAMs with 16 > bits of data (this means you can have 32 or 64M maximum depending on which > parts you use).I have a bunch of SDRAM DIMMs but they are a bit... complex. also, tracing where each pin goes to which pad is going to be... tedious. it's probably not less complex than soldering directly to the pins... (except for the size but I have one or two ideas)> Now how you connect this piece of board to the other > still remains unclear, of course;I won't risk the FPGA board, i'll use 2.54mm connectors. If something goes wrong with the FPGA, or if modifications are needed, i'll just unplug.> using many evenly spread GND wires > between the two might help, but you won't know if it will work until > it works...sure :-) hmmmmm I slowly realise that it's obviously weird, but not impossible ... I think that I've seen worse, maybe at http://www.fpga4fun.com and other places. I just want to get the SDRAM pins, functions, timings and sequences right before I spend time making a (proto) PCB... regards,> Dimiteryg -- http://ygdes.com / http://yasep.org
Reply by ●January 22, 20092009-01-22
On Jan 21, 7:34=A0pm, whygee <why...@yg.yg> wrote:> CBFalconer wrote: > > To evaluate the effects of wire length, consider that 1 foot (1/3 > > meter) of wire represents about 1 nS in a vacuum. =A0Probably closer > > to 2 nS in your environment. =A0100 MHz chips are cycling in no more > > than 10 nS. > > Yes but other issues arise. > And I've read everywhere that SDRAMs are difficult to use... > getting pas initialisation is often described as ... a lot of work. > > > Also bear in mind that you have to provide the appropriate signals > > and addresses to refresh the memory at some interval. > > that's what bothers me most. > I'll check if there is an auto-refresh mode that cuts my efforts.Yes, they all have auto refresh, but it does require you to create the refresh cycle, the SDRAM provides the address using an internal counter. I don't remember the details, but the refresh cycle is just like a RAS cycle, IIRC, it just has a different signal asserted. Have you looked for IP anywhere? opencores.org may have an SDRAM controller.> Also : > If I scan the buffers sequentially at a known rate > (this is for audio samples) then I could arrange the interleaving > in such a way that no explicit refresh is needed. > > I suspect that this method is used in video adapters, > since at least one old personal computer (a french 6809-based > thing popular around 1984) uses this idea. > So I will try to combine both refresh and normal scan...If it is not easy, don't bother. It can make your design more complex than needed. The refresh cycle is very simple and only takes one clock cycle every 15 us I think.> > =A0See the data sheets for this. > > The circuitry is a complication, not present in static memory chips. > > Static RAMs also have their gotchas... > > > The variation in delays through this > > circuitry also need to get absorbed in that 10 nS window. > > Certainly. > Correct data latching is necessary. > > Damn, I'm almost afraid of what I've got myself into...
