DDR / DDR2 memory controllers

David Kinsell wrote:
> > Yes, I've noticed this too.  My I/O is 16-bits. 
> > I was thinking about maybe a buffer or bus switch
> > to toggle between bus "banks" to get the full
> > capacity.
> 
> I think you'd need to pack 4 writes into a 64 bit
> buffer, and write it at once.

Hmmm... I need to explore this a bit more.

On the surface, it seems like manipulating the CS lines (there are 2 per
DIMM for high vs. low data groups), plus the DQM lines (one per chip),
one might be able to read and write to individual chips, all sharing the
same 8 I/O lines.  (Although needing an aweful lot of contol lines.)

I'm not sure what effect this might have on issuing commands to the
DRAMs, but if they really act like individual x8 chips, this should
work.


> Intel has documents on their site showing the
> architecture for the various DIMM's.  It's a good
> starting place.

Thanks for the pointer!


> > Where does the complexity lie?
> 
> There's the black magic factor.  There's very little
> design margin in DRAM implementations.
[...]
> Memory design is not nearly as Plug and Play as you
> might imagine.

Got it, thanks.  This makes more sense.


> For a practical product, I'd look at individual
> chips, either DDR or pseudo-static.

I'm dabbling with individual chips now, but at least Micron is warning
on long-term availability of SDR, since the industry is moving to DDR
and beyond (which pushes this project into a whole new class of MCU).

I'm guessing that DIMMs may remain available for some time to support
the consumer market.  However, the cost of the socket is very high -
over $20 in low quantity, I recall.  And despite consumer volumes on
DIMMs, it seems an equal quantity of chips is actually cheaper for now.

An interesting project regardless...

Thanks again!
Richard