Best way to interface the AD7691 ADC to AT91SAM9RL ARM processor running Linux

>
> According to the AD7691 data sheet, there is no problem shifting more than
> 18 bits, so it should be possible to use h/w spi for shifting 3 bytes and
> then manipulate in s/w.
>

That sounds good, Robert; thank you for pointing this out in the context 
of my application.

Nicholas

2010-11-03 01:40, Nicholas Kinar skrev:
> Hello,
>
> I would like to interface five AD7691 18-bit ADCs to a Atmel ARM
> processor (AT91SAM9RL) running the Linux operating system. The processor
> will be clocked at a speed of ~200 MHz, and I would like to sample the
> ADCs at a rate of 10 kHz.
>
> The AD7691 ADC
> (http://www.analog.com/static/imported-files/data_sheets/AD7691.pdf) has
> a conversion pin CNV. A conversion is triggered by a rising pulse on
> this pin. The data is then read from each ADC using an SPI interface.
>
> The AT91SAM9RL processor has only one SPI bus without FIFO.
>
> What is the best way to do this using a Linux kernel driver? Two likely
> scenarios:
>
> (1) All ADCs are wired to the SPI bus, and each ADC has a /CS pin wired
> to the AT91SAM9RL processor. The AT91SAM9RL toggles the CNV pin so that
> the ADCs are read at a 10 kHz sampling rate. The AT91SAM9RL then selects
> each /CS pin of the five ADCs, and reads each slave in order.
>
> BUT, does writing a Linux kernel driver guarantee that the processor can
> toggle the CNV pin and then read the five ADCs in sequential order at a
> rate of 10kHz?
>
> (2) The AD7691 can be daisy chained. Would it be possible to daisy-chain
> all five ADCs and then read the data as a big (18 bit)(5) = 90 bit
> transfer?
>
> What type of kernel driver would be most appropriate, and what would be
> the best way to wire up the ADCs if I am to use a kernel driver for the
> AD7691 ADC running on a AT91SAM9RL Linux board?
>
> Nicholas

I think you may want to look at the AT91SAM9G45 instead of the AT91SAM9RL64.
This part has dual SPI, and on top of that, each USART has a
an SPI Master mode for a total of 6 SPI Masters.
It also supports DDR-2 memories which will make the memory
subsystem much cheaper than that of the SAM9RL64 which will have to use
SDRAM.

An alternative , probably better, is to use the SSC.
This should allow you to use the daisy chain mode of the ADCs
on a single serial interface with DMA support.

The rising edge of the TX framesync is connected to CNV,
The RX Framesync, can be connected to the SPI chip selects


Best Regards
Ulf Samuelsson

>
> I think you may want to look at the AT91SAM9G45 instead of the
> AT91SAM9RL64.
> This part has dual SPI, and on top of that, each USART has a
> an SPI Master mode for a total of 6 SPI Masters.
> It also supports DDR-2 memories which will make the memory
> subsystem much cheaper than that of the SAM9RL64 which will have to use
> SDRAM.
>
> An alternative , probably better, is to use the SSC.
> This should allow you to use the daisy chain mode of the ADCs
> on a single serial interface with DMA support.
>
> The rising edge of the TX framesync is connected to CNV,
> The RX Framesync, can be connected to the SPI chip selects
>
>
> Best Regards
> Ulf Samuelsson
>

Thanks, Ulf; this is greatly appreciated, and I have to admit that the 
AT91SAM9G45 part looks very interesting!

I also like the idea of daisy-chaining the ADCs and connecting them all 
to the SSC bus.

Looking again at the AD7691 datasheet 
(http://www.analog.com/static/imported-files/data_sheets/AD7691.pdf), 
how might I wire up the daisy-chained ADCs to the SSC bus?

Pages 22-23 of the AD7691 datasheet shows the connections required for 
daisy-chain mode.  Taking into consideration your recommendation, I 
think that the following pin mapping table would work.

TABLE:

Processor SSC bus ==> ADC
------------------------------
TX-FRAMESYNC ==> CNV
RX           ==> SDO of last ADC
CLK          ==> CLK


Could I use a GPIO as an interrupt (IRQ), as shown on page 23 of the 
AD7691 datasheet?

How would I set up a Linux driver to take a sample at a 1 kHz rate?  I 
suppose that TX-FRAMESYNC would be toggled and then allowed to stay high 
while the data would be read from the ADCs. The data would then be 
transferred directly into memory using DMA.

Is there support for this type of operation in the Linux kernel?  Is it 
possible to read arbitrary-length words from the SSC bus?


Nicholas