On 2011-03-15, Like2Learn <like2learn@live.ca> wrote:> On Mar 15, 8:23?am, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> > wrote: >> In comp.arch.embedded, >> >> Mark Borgerson <mborger...@comcast.net> wrote: >> >> > This is really going to slow down a 100mHz processor. >> >> With these numbers, I don't expect the processor will signifficantly slow >> down. What's a mere 800ns on a 10s instruction cycle (assuming one >> cycle/clock). ;-) > > Could you please let me know where the 10s instruction cycle come > from? Is it 10ns?It is a literal interpetation of a quoted speed of 100mHz: i.e. 100 millihertz, rather than 100MHz, 100 megahertz. -- Andrew Smallshaw andrews@sdf.lonestar.org
Question about the speed of SPI RAM
Started by ●March 14, 2011
Reply by ●March 15, 20112011-03-15
Reply by ●March 15, 20112011-03-15
On Mar 15, 7:25=A0pm, Like2Learn <like2le...@live.ca> wrote:> On Mar 14, 5:26=A0pm, Like2Learn <like2le...@live.ca> wrote: > > > Hi there, > > > We found we had to add an external RAM (SRAM or SDRAM) at the late > > stage of electrical design. Basically there are only 2 GPIO pins still > > available, otherwise the RAM has to share with other peripherals, such > > as SPI and I2C. I prefer to connect the external RAM with SPI bus. > > However, I am not sure if it is fast enough for RAM read/write. Does > > anybody know the typical speed of SPI RAM read/write? Does it meet the > > requirement for a device similar to an ethernet switch plus a sensor? > > The data collected by the sensor is about 1K bytes per second. > > Some background info: The CPU chosen is 32-bit, and can deliver 165 > > DMIPS at a maximum operating frequency of 100MHz. =A0Our application > > needs 1ms time tick. > > > Thank you. > > Has anybody know any other way to connect the RAM to the processor > with only a few IO pins, and run faster than SPI? > > tHANKS.SPI has very low overhead for a given serial bit rate, I would guess no.
Reply by ●March 16, 20112011-03-16
On 15/03/2011 14:32, Mark Borgerson wrote:> In article<4d7f09e0$0$41117$e4fe514c@news.xs4all.nl>, usenet+5@c- > scape.nl says... >> >> On 03/15/2011 12:26 AM, Like2Learn wrote: >>> Hi there, >>> >>> We found we had to add an external RAM (SRAM or SDRAM) at the late >>> stage of electrical design. Basically there are only 2 GPIO pins still >>> available, otherwise the RAM has to share with other peripherals, such >>> as SPI and I2C. I prefer to connect the external RAM with SPI bus. >>> However, I am not sure if it is fast enough for RAM read/write. Does >>> anybody know the typical speed of SPI RAM read/write? Does it meet the >>> requirement for a device similar to an ethernet switch plus a sensor? >>> The data collected by the sensor is about 1K bytes per second. >>> Some background info: The CPU chosen is 32-bit, and can deliver 165 >>> DMIPS at a maximum operating frequency of 100MHz. Our application >>> needs 1ms time tick. >> >> How big does the SRAM need to be ? >> >> If you only need a modest size, here's a couple of reasonably priced parts: >> >> Microchip 23K640 - 64Kb, 20MHz SPI >> Microchip 23K256 - 256Kb, 20MHz SPI > > SPI RAM is going to truly suck if it is really used as random-access > memory. If randomly addressing word variables, you need to send two > or more bytes of address for each word retrieved. With 20MHz SPI > clock speed, each address or data byte takes 200nSec. Retrieving > a randomly addressed word takes 4 byte transfers, or 800nSec. This is > really going to slow down a 100mHz processor. >The real-world numbers are a lot worse than that. First, unless I am making a silly mistake, an 8-bit byte transfer will take 400 ns at 20 MHz spi clock. Then to access data on the second chip you mentioned above, you are going to need at least one "command" byte and three address bytes, giving four transfers before the data itself. You also have overhead for things like the chip select and setup. So in practice you are looking at around 2 us per transaction, plus 400 ns per byte transferred. The key to making this efficient is to overlap the transfers with other work. If possible, use DMA to handle the transfers. So when you want to read data, set the read transfer in action as early as possible, and the DMA will handle the data while your processor does something else. Keep your data in the SRAM in blocks (typically an array of structs) so that you can do your transfers using only a few transactions. For example, if your program has a sampling function that runs at 1 KHz and collects data, then needs to write it out to SRAM, you can set that writeout in action at the end of the sampling function. Your processor can do other things while the DMA handles the transaction, and it doesn't matter much how long that takes.
Reply by ●March 16, 20112011-03-16
In article <42656$4d7f765e$5f6173bc$14245@abuse.newsxs.nl>, stef33d@yahooI-N-V-A-L-I-D.com.invalid says...> > In comp.arch.embedded, > Mark Borgerson <mborgerson@comcast.net> wrote: > > > > SPI RAM is going to truly suck if it is really used as random-access > > memory. If randomly addressing word variables, you need to send two > > or more bytes of address for each word retrieved. With 20MHz SPI > > clock speed, each address or data byte takes 200nSec. Retrieving > > a randomly addressed word takes 4 byte transfers, or 800nSec. This is > > really going to slow down a 100mHz processor. > > With these numbers, I don't expect the processor will signifficantly slow > down. What's a mere 800ns on a 10s instruction cycle (assuming one > cycle/clock). ;-)Good Catch! those dang millis and megas just keep switching places on my keyboard! Mark Borgerson
Reply by ●March 16, 20112011-03-16
In article <cd34336f-8c99-4127-a290-ebe78cea0ed0 @n2g2000prj.googlegroups.com>, like2learn@live.ca says...> > On Mar 15, 7:32�am, Mark Borgerson <mborger...@comcast.net> wrote: > > In article <4d7f09e0$0$41117$e4fe5...@news.xs4all.nl>, usenet+5@c- > > scape.nl says... > > > > > > > > > > > > > > > > > On 03/15/2011 12:26 AM, Like2Learn wrote: > > > > Hi there, > > > > > > We found we had to add an external RAM (SRAM or SDRAM) at the late > > > > stage of electrical design. Basically there are only 2 GPIO pins still > > > > available, otherwise the RAM has to share with other peripherals, such > > > > as SPI and I2C. I prefer to connect the external RAM with SPI bus. > > > > However, I am not sure if it is fast enough for RAM read/write. Does > > > > anybody know the typical speed of SPI RAM read/write? Does it meet the > > > > requirement for a device similar to an ethernet switch plus a sensor? > > > > The data collected by the sensor is about 1K bytes per second. > > > > Some background info: The CPU chosen is 32-bit, and can deliver 165 > > > > DMIPS at a maximum operating frequency of 100MHz. �Our application > > > > needs 1ms time tick. > > > > > How big does the SRAM need to be ? > > > > > If you only need a modest size, here's a couple of reasonably priced parts: > > > > > Microchip 23K640 - 64Kb, 20MHz SPI > > > Microchip 23K256 - 256Kb, 20MHz SPI > > > > SPI RAM is going to truly suck if it is really used as random-access > > memory. �If randomly addressing word variables, you need to send two > > or more bytes of address for each word retrieved. �With 20MHz SPI > > clock speed, each address or data byte takes 200nSec. �Retrieving > > a randomly addressed word takes 4 byte transfers, or 800nSec. �This is > > really going to slow down a 100mHz processor. > > > > Mark Borgerson- Hide quoted text - > > > > - Show quoted text - > > Good point. However, I believe the additional memory is likely to be > used only occasionally and temporarily, to swap data back and forth to > the main memory. The firmware is likely to be executed at the main > memory only. So maybe the performance is not too bad.OK. I've used SPI NVRAM in similar situations as buffer memory between two processors. If you use SPI memory in situations where you can transfer larger blocks of data back and forth between normal RAM it is a lot more useful. Mark Borgerson
Reply by ●March 17, 20112011-03-17
On Mar 16, 12:25=A0pm, Like2Learn <like2le...@live.ca> wrote:> On Mar 14, 5:26=A0pm, Like2Learn <like2le...@live.ca> wrote: > > > Hi there, > > > We found we had to add an external RAM (SRAM or SDRAM) at the late > > stage of electrical design. Basically there are only 2 GPIO pins still > > available, otherwise the RAM has to share with other peripherals, such > > as SPI and I2C. I prefer to connect the external RAM with SPI bus. > > However, I am not sure if it is fast enough for RAM read/write. Does > > anybody know the typical speed of SPI RAM read/write? Does it meet the > > requirement for a device similar to an ethernet switch plus a sensor? > > The data collected by the sensor is about 1K bytes per second. > > Some background info: The CPU chosen is 32-bit, and can deliver 165 > > DMIPS at a maximum operating frequency of 100MHz. =A0Our application > > needs 1ms time tick. > > > Thank you. > > Has anybody know any other way to connect the RAM to the processor > with only a few IO pins, and run faster than SPI? > > tHANKS.Your choices would include change any existing i2c memory to Ramtron FRAM, as that can work as SRAM at moderate rates, and also as EEPROM SPI is usually the fastest serial link, to some tens of MHz, but there are QuadSPI devices (in Flash mainly; I think Cypress were talking of NvSRAM in QuadSPI soon ?) Of course, Quad SPI needs more pins (4 data lines), and a processor with a quad capable peripheral.
