Cortex-M3 vs PIC32 divide instruction

Started by Jon Kirwan September 6, 2011
On Sep 12, 1:35=A0am, Jon Kirwan <j...@infinitefactors.org> wrote:

> But nothing under $2, or close, showed up on the first sorted page.
Well, yes, those numbers are Market-droid claims, (but they are in the 1K column, not the usual 6 digit claims...) ADI here says $1.99/1K and $2.99/100 http://www.analog.com/en/processors-dsp/blackfin/adsp-bf592/processors/prod= uct.html for a 200MHz/400MMAC part, with good 32 bit timers
> But a closer reading of your comment might be that you mean > to talk about cases where the processor itself is built on a > fast, clocked process, let's say 400MHz given worst case > pathways and pipelining limits (M4k at 90nm.) =A0But that the > flash and cache (and, I suppose, also the necessity these > days for marketing purposes that a microcontroller include > bullet-proof, class-A crystal drivers rather than specify > some more complex high-speed design) may limit the useful > speed to something less, say 80MHz. =A0(Though I've read > someone to say they've clocked the PIC32 at 120MHz, just had > to set wait states for the flash.) =A0That in this case, say, a > sampling ADC of the SAR style might be clocked still at > 400MHz to process a captured sample at whatever resolution > without regard to the CPU clock rate? =A0Is that it?
Close enough; There may be a 80MHz imposed by flash, or I might want to clock the CPU at 20MHz for power-budget reasons. It is silly that I am then imposed a ceiling of 50ns for peripherals. Some parts (not many) DO allow faster peripheral clocks than the core. eg I've seen recent claims of 256Mhz timers on XMega, and some MSP430s and some parts use delay line calibration schemes to get to 1ns or below, on PWM edge resolution, and a subset of those also give higher resolution capture.. I think I've seen a couple that use a high frequency clock for UARTS, as those can nudge over 20MHz these days. Then there are nice parts like the Silabs Si5351A, (close to $1), which can output (almost) any 3 CLK's up to 160MHz, using fractional synthesisers, and a 600-900MHz VCO+Xtal. These can help solve some clock-conflicts. -jg