On Thu, 27 Jan 2005 19:54:52 GMT, Tauno Voipio <tauno.voipio@iki.fi.NOSPAM.invalid> wrote:>Clive Wilson wrote: >> "Grzegorz Mazur" <easy2find@the.net> wrote in message >> news:ctalfl$ja4$1@julia.coi.pw.edu.pl... >> >>>Clive Wilson wrote: >>> >>>>Dear All, >>>> >>>>I'm looking for a cheap 8/16 bit uP/uC that has an external bus >>>>interface, so that about 256k of SRAM can be addressed. It needs to have >>>>on-board Flash, around 32k would be good. The device doesn't need many >>>>GPIO pins, perhaps 5 or so just in case. It doesn't need ADC/DACs, USB >>>>etc like all the manfs seem to throw in them these days. It will be >>>>running a TCP/IP stack with link layer to connect to modem, so the >>>>processor also needs a UART. Price needs to be <$1.50 or so, in 100k >>>>quantities. >>>> >>>>Any ideas? To recap: >>> >>>And what's the problem with 32-bit ones? Too easy memory addressing or too >>>high processing speed? >>> >>>Seriously, at that price you could probably dream of not-too-fast '51 and >>>using external memory above 64K is a nighmare on 8/bit MPUs. Your specs >>>can be easily met by almost any ARM and many Renesas H8 chips at a >>>slightly higher price. Anyway I don't believe you will get a contemporary >>>'51 chip with 2 UARTS at $1.5. >> >> >> Grzegorz, >> >> Thanks for your reply. Two points I'd like to discuss a little more: >> >> 1. You mention that using external memory above 64K is a nighmare on 8 bit >> MPUs. Why is this? As long as the data is treated as 'far' by the C compiler >> (no asm please!), then the compiler will take care of the paging. Admittedly >> it takes processor cycles to achieve this. Is this the angle you were coming >> from, or did you have other reservations? > >An 8 bit micro will have only 16 address lines -> maximum addressable >range = 0 to 65535 (0x0 to 0xffff) without page switching or similar >tricks. The paging is a nightmare, regardless whether it's done by >the compiler/linker/run-time combination or the programmer. > >> 2. You seem to suggest that I could get a sufficiently-spec'ed ARM for less >> than an H8? Really? Which vendor(s) did you have in mind? > >My vote to an Atmel AT91.I would imagine that in most case, if you need >64K, the bulk of it is not for general storage but for some particular data, that could easily be accessed via a special routine that handles the paging etc.
Cheap 8-bit micro with external bus interface?
Started by ●January 27, 2005
Reply by ●January 28, 20052005-01-28
Reply by ●January 28, 20052005-01-28
"Paul Burke" <paul@scazon.com> wrote in message news:35ucfbF4qpd1gU1@individual.net...> Tauno Voipio wrote: >> >> An 8 bit micro will have only 16 address lines -> maximum addressable >> range = 0 to 65535 (0x0 to 0xffff) without page switching or similar >> tricks. The paging is a nightmare, regardless whether it's done by >> the compiler/linker/run-time combination or the programmer. >> > > I've missed the start of this, but a lot depends on how the OP wants to > use the RAM. It's easy enough to set up a paged access scheme for any > amount of RAM with an external latch for the high-order addresses. Of > course, there is a performance hit, and the compiler can't deal with it > directly. But I can't imagine that his app is using that much RAM in the > ordinary way anyway, not in an 8 bit system.Paul, You're quite right. The large RAM area is to be used for buffering data received through one comms medium, checking it for integrity, then passing on via another comms medium. The app that controls all this will, it is hoped, fit in the on-chip SRAM. Still, if the data is larger than 64k then the page switching will still be a nuisance. I quite like Ulf's suggestion of an AT91R40008 which has 256k SRAM on-board, this saves the cost of the SRAM devices. The question is will the device come in under the total budget? I'll have to see... CTW
Reply by ●January 28, 20052005-01-28
Reply by ●January 28, 20052005-01-28
> Paul, > > You're quite right. The large RAM area is to be used for buffering data > received through one comms medium, checking it for integrity, then passing > on via another comms medium. The app that controls all this will, it is > hoped, fit in the on-chip SRAM. Still, if the data is larger than 64k then > the page switching will still be a nuisance. > > I quite like Ulf's suggestion of an AT91R40008 which has 256k SRAMon-board,> this saves the cost of the SRAM devices. The question is will the device > come in under the total budget? I'll have to see... > > CTWDrop me an email (remove the hyphens) and I'll talk to some guys to find out whats possible. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic AB "Clive Wilson" <clive@nowhere.invalid> skrev i meddelandet> >
