Pc104 interfacing

Started by Max March 24, 2004
Hi all,

I use a CPLD to generate interrupt in a PC104 system. It work's fine.
The question is:
is correct connect CPLD output diretly to PC104 IRQ input (i don't need
interrupt sharing)? Or i need other hardware (pull-up resistor or other)  ?

Thank's in advance

Max


Max wrote:

> Hi all, > > I use a CPLD to generate interrupt in a PC104 system. It work's fine. > The question is: > is correct connect CPLD output diretly to PC104 IRQ input (i don't need > interrupt sharing)? Or i need other hardware (pull-up resistor or other) ? > > Thank's in advance > > Max > >
Maybe you don't to need to share at this time, but what for the future ! Your interrupt signal schould be driven by an open-drain and an pull-up. Depending on your CPLD family, you can map internal pull-up. But if you have place on the pcb, please add the pattern for an external pull-up. In your VHDL, you have : irq_out <= '0' WHEN an_condition ELSE '1' ; for an open-drain, you just have to change by irq_out <= '0' WHEN an_condition ELSE 'Z' ; -- you need here an pull-up to fix '1'; Regards, Laurent Gauch www.amontec.com
Max wrote:

> I use a CPLD to generate interrupt in a PC104 system. It work's fine. > The question is: > is correct connect CPLD output diretly to PC104 IRQ input (i don't > need interrupt sharing)? Or i need other hardware (pull-up resistor > or other) ?
Hello Max, No, you don't need other hardware. No resistors, no open-collector outputs. Karl Olsen
laurent gauch wrote:
> > Max wrote: > > > Hi all, > > > > I use a CPLD to generate interrupt in a PC104 system. It work's fine. > > The question is: > > is correct connect CPLD output diretly to PC104 IRQ input (i don't need > > interrupt sharing)? Or i need other hardware (pull-up resistor or other) ? > > > > Thank's in advance > > > > Max > > > > > > Maybe you don't to need to share at this time, but what for the future ! > > Your interrupt signal schould be driven by an open-drain and an pull-up. > > Depending on your CPLD family, you can map internal pull-up. But if you > have place on the pcb, please add the pattern for an external pull-up. > > In your VHDL, you have : > > irq_out <= '0' WHEN an_condition ELSE '1' ; > > for an open-drain, you just have to change by > > irq_out <= '0' WHEN an_condition ELSE 'Z' ; > -- you need here an pull-up to fix '1';
Time out Laurent! This is exactly wrong. The IRQ is an active *HIGH* signal. So you have to drive the signal high when asserted, hi-z when not asserted and use a pull-down resistor as the common element to assert a low on an open bus. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
I'm also trying to design a PC104 (ISA) bus board.
I will interface an ADC and FIFO buffer to PC104 (ISA) bus.
I need to control ADC to digitize input signal in a burst and store the
converted data into a FIFO.
When FIFO is full, I need to generate an interrupt to signal the PC104 for
data transfer.
Unfortunatelly I do not have experience with CPLDs (yet).
Is it possible if you can share your CPLD design with us so that we can
learn from your experience?

Regards,


> Hi all, > > I use a CPLD to generate interrupt in a PC104 system. It work's fine. > The question is: > is correct connect CPLD output diretly to PC104 IRQ input (i don't need > interrupt sharing)? Or i need other hardware (pull-up resistor or other)
?
> > Thank's in advance > > Max > >
"k" <k@k.com> ha scritto nel messaggio
news:4062da30$0$25292$afc38c87@news.optusnet.com.au...
> I'm also trying to design a PC104 (ISA) bus board. > I will interface an ADC and FIFO buffer to PC104 (ISA) bus. > I need to control ADC to digitize input signal in a burst and store the > converted data into a FIFO. > When FIFO is full, I need to generate an interrupt to signal the PC104 for > data transfer. > Unfortunatelly I do not have experience with CPLDs (yet). > Is it possible if you can share your CPLD design with us so that we can > learn from your experience? > > Regards,
Hi, my board will interface a Philips SJA1000 CAN controller to PC104 bus; CPLD is used first af all to make other things (address docode for other chip, clock divider,ecc...). I need to invert SJA1000 INT line and connect it to PC 104 IRQ line so i use a gate of the CPLD (...but in the same way i can use a 74HC04: i think that my experience will not help you....) Regards, Max