Software to generate jed file for PAL chips

Hi,

I need to program a couple of old small assorted brand PAL (including
GAL) chips. Is there any free software tool that can generate jed
files from Verilog (or ABEL and schematic) entry so that I can export
to a universal programmer for downloading purpose? Thanks for any
help.

CFF

CFF wrote:
> Hi,
> 
> I need to program a couple of old small assorted brand PAL (including
> GAL) chips. Is there any free software tool that can generate jed
> files from Verilog (or ABEL and schematic) entry so that I can export
> to a universal programmer for downloading purpose? Thanks for any
> help.
> 
> CFF

  Xilinx used to allow this, but it would not surprise me if that option
has 'long gone'...
  Atmel have WinCUPL, free on their website, which is similar to ABEL, 
and that _does_ target the generic SPLDs of 16V8/20V8/22V10.
-jg

HI,
there is an ABEL achive at:
http://www.people.fas.harvard.edu/~thayes/ABEL_download/

I guess it is an old ODS version and havent tried it.
But : better than none.

grtnx
/jan

CFF <cffung@myrealbox.com> schrieb in im Newsbeitrag:
2560187f.0403122139.20c0c145@posting.google.com...
> Hi,
>
> I need to program a couple of old small assorted brand PAL (including
> GAL) chips. Is there any free software tool that can generate jed
> files from Verilog (or ABEL and schematic) entry so that I can export
> to a universal programmer for downloading purpose? Thanks for any
> help.
>
> CFF

"CFF" <cffung@myrealbox.com> schreef in bericht
news:2560187f.0403122139.20c0c145@posting.google.com...
> Hi,
>
> I need to program a couple of old small assorted brand PAL (including
> GAL) chips. Is there any free software tool that can generate jed
> files from Verilog (or ABEL and schematic) entry so that I can export
> to a universal programmer for downloading purpose? Thanks for any
> help.
>
> CFF


Lattice has a complete package for it. The version I used for a long time
supported also the old AMD components. Don't know about their current
package.

petrus


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Jan Homuth wrote:

> HI,
> there is an ABEL achive at:
> http://www.people.fas.harvard.edu/~thayes/ABEL_download/
> 
> I guess it is an old ODS version and havent tried it.
> But : better than none.

  The comment at that URL says it is a restricted version, and
they need another LAB Abel to create JED files...
  Pity, a use-able download version of ABEL would make a good, stable
teaching solution.
-jg

On 12 Mar 2004 21:39:06 -0800, cffung@myrealbox.com (CFF) wrote:

>Hi,
>
>I need to program a couple of old small assorted brand PAL (including
>GAL) chips. Is there any free software tool that can generate jed
>files from Verilog (or ABEL and schematic) entry so that I can export
>to a universal programmer for downloading purpose? Thanks for any
>help.
>
>CFF

Google "palasm"; it's still around. Here's one:

http://www.brouhaha.com/~eric/retrocomputing/mmi/palasm/


John

Jim, I just found a full working (good old DOS) ABEL4 toolchain.

The thing is about 7.5 Megs zipped with documentation.

I am not sure about copyright issues.
If these can be resolved AND:
if someone is willing to provide some webspace I'd be willing to donate the
archive.
ABEL is a quick, nice and basic way to build logic for PLD and GAL and it is
not limited to a specific vendor or device family.

grtnx
/jan


Jim Granville <no.spam@designtools.co.nz> schrieb in im Newsbeitrag:
7CM4c.1155$u%1.187853@news02.tsnz.net...
> Jan Homuth wrote:
>
> > HI,
> > there is an ABEL achive at:
> > http://www.people.fas.harvard.edu/~thayes/ABEL_download/
> >
> > I guess it is an old ODS version and havent tried it.
> > But : better than none.
>
>   The comment at that URL says it is a restricted version, and
> they need another LAB Abel to create JED files...
>   Pity, a use-able download version of ABEL would make a good, stable
> teaching solution.
> -jg
>

On 12 Mar 2004 21:39:06 -0800, cffung@myrealbox.com (CFF) wrote:
>I need to program a couple of old small assorted brand PAL (including
>GAL) chips. Is there any free software tool that can generate jed
>files from Verilog (or ABEL and schematic) entry so that I can export
>to a universal programmer for downloading purpose? Thanks for any
>help.
I use WinCUPL, it is available for free. Works fine.

Regards,

Pieter Hoeben
http://www.hoeben.com