Processors who's stack grows up

On Fri, 07 Jan 2005 14:32:13 +0000, Robert Kaiser wrote:

> In article <41dabc9a$1@solnews.wv.mentorg.com>,
> 	"Adam Messer" <adam_messer@mentor.com> writes:
>> We have a fair amount of code
>> in our system that accommodates stacks that grow up. If we can't find a
>> reasonable number of processors who's stack does grow up we will remove that
>> code.
> 
> The MIPS processor doesn't really have a notion of a stack (and I
> suspect this applies to some other RISC architectures as well).
> It is up to the compiler to implement a stack and so a compiler 
> writer can choose to let the stack grow up or down. However, I'm not
> aware of any MIPS compilers that actually let the stack grow up.

I've never used one, but I believe that the normal convention for
HP-PA under HP-UX is for stacks to grow upwards.

-- 
Andrew

On Tue, 04 Jan 2005 21:26:40 GMT, CBFalconer <cbfalconer@yahoo.com>
wrote:

> Adam Messer wrote:
> > 
> > I am the lead engineer on the Nucleus Plus RTOS. One of my coworkers
> > asked me if I knew any processors that had a stack that grows up.
<snip>
> 
> The HP3000.

And, for completeness, an architecture that was if not quite descended
from at least inspired by the HP 3000, Tandem^WCompaq^WHP NonStop,
which was still built and sold as recently as IIRC 1992, and userland
software for which is still supported in emulation on the successor
TNS/R systems since Tandem shops tend to be very slow to change their
business-critical applications. But the OS now is all 'native' MIPS
with downward stack, and even in the days of TNS hardware no one with
sense would have bought it to run a non-Tandem OS and throw away the
fault-tolerance and support features they paid a hefty premium for.

Also, equally irrelevantly, the PDP-10 doesn't have any "hardware"
stack for interrupts, but can use any GPR (except R0? I forget) as a
pointer to an upward-growing and (optionally) length-checked stack.
According to the folks in alt.sys.pdp10 there are actually a few clone
hardware systems still in use, as well as rather more folks using
(several) emulators, but again those systems are kept in existence
(only) to run old software and they wouldn't want to run Nucleus.

- David.Thompson1 at worldnet.att.net

Hello,

Robert Kaiser wrote...
> The MIPS processor doesn't really have a notion of a stack (and I
> suspect this applies to some other RISC architectures as well).
> It is up to the compiler to implement a stack and so a compiler 
> writer can choose to let the stack grow up or down.

If the MIPS doen't have a notion of a stack, do they have call/ret 
instructions? What about interrupts? The interrupted location must be 
saved somewhere.

- Heinz

Heinz Saathoff wrote:
> Hello,
> 
> Robert Kaiser wrote...
> 
>>The MIPS processor doesn't really have a notion of a stack (and I
>>suspect this applies to some other RISC architectures as well).
>>It is up to the compiler to implement a stack and so a compiler 
>>writer can choose to let the stack grow up or down.
> 
> 
> If the MIPS doen't have a notion of a stack, do they have call/ret 
> instructions? What about interrupts? The interrupted location must be 
> saved somewhere.
> 

In RISC processors it is a common method to have
special registers which save the interrupted state,
including the return location.

As an example, in ARM processors there are saved
PSR and exception state link registers to save
the previous processor status and return location.

The interrupt handler software may decide to still
save the state into a stack, but it is then entirely
managed by the software handler.

-- 

Tauno Voipio
tauno voipio (at) iki fi

"Heinz Saathoff" <hsaat@despammed.com> wrote
> Robert Kaiser wrote...
> > The MIPS processor doesn't really have a notion of a stack (and I
> > suspect this applies to some other RISC architectures as well).
> If the MIPS doen't have a notion of a stack, do they have call/ret 
> instructions? What about interrupts? The interrupted location must be 
> saved somewhere.

They get younger every year ...

http://www.cs.clemson.edu/~mark/subroutines.html

The stack, as in "SP->memory", in a non-Burroughs* machine
(see below) is a recent circa 1970 creation.  

The traditional method (like we got traditions in computer design)
of returning from subroutines was by forming a linked list.  Sometimes
by such subtle methods as writing a JMP instruction to the caller's
"return-to" address at the end of the called subroutine - remember 
all code was in core ("RAM" for the young'ns) - this method is 
not recommended for recursion.

IBM (?) came up with the idea of linking registers rather than
using code modification when subroutines are called.

Register linkage re-appeared in the TI-9900 micro (others?) and some
modern primitive instruction set micros as MIPS (above).

* The early Burroughs machines are a must see:

http://www.cs.virginia.edu/brochure/images/manuals/b5000/descrip/descrip.html

A machine designed to run Algol, c. 1958.

-- 
Nicholas O. Lindan, Cleveland, Ohio
Consulting Engineer:  Electronics; Informatics; Photonics.
Remove spaces etc. to reply: n o lindan at net com dot com
psst.. want to buy an f-stop timer? nolindan.com/da/fstop/

Nicholas O. Lindan wrote...
> "Heinz Saathoff" <hsaat@despammed.com> wrote
> > If the MIPS doen't have a notion of a stack, do they have call/ret 
> > instructions? What about interrupts? The interrupted location must be 
> > saved somewhere.
> 
> They get younger every year ...

Or you get older every year ;-)

 
> http://www.cs.clemson.edu/~mark/subroutines.html
> 
> The stack, as in "SP->memory", in a non-Burroughs* machine
> (see below) is a recent circa 1970 creation.  

Yes, I'm too young to know that (was 10 years old that year). 
Thank's for this historic infos.

- Heinz

In article <JNCEd.3322$KJ2.826@newsread3.news.atl.earthlink.net>,
	"Nicholas O. Lindan" <see@sig.com> writes:
>
> The traditional method (like we got traditions in computer design)
> of returning from subroutines was by forming a linked list.  Sometimes
> by such subtle methods as writing a JMP instruction to the caller's
> "return-to" address at the end of the called subroutine -

That would require the caller to know the end of the subroutine.

You are probably referring to the CDC. It would write a jump back
to the caller at the *first* word of the callee and begin execution
at the 2nd word.

Dick Wesseling wrote:
> In article <JNCEd.3322$KJ2.826@newsread3.news.atl.earthlink.net>,
> 	"Nicholas O. Lindan" <see@sig.com> writes:
> 
>>The traditional method (like we got traditions in computer design)
>>of returning from subroutines was by forming a linked list.  Sometimes
>>by such subtle methods as writing a JMP instruction to the caller's
>>"return-to" address at the end of the called subroutine -
> 
> 
> That would require the caller to know the end of the subroutine.
> 
> You are probably referring to the CDC. It would write a jump back
> to the caller at the *first* word of the callee and begin execution
> at the 2nd word.

I believe a pdp 8 did the same thing.  The
return was an indirect jump to the first word.

On 2005-01-16, Dick Wesseling <free@securityaudit.val.newsbank.net> wrote:

>> The traditional method (like we got traditions in computer design)
>> of returning from subroutines was by forming a linked list.  Sometimes
>> by such subtle methods as writing a JMP instruction to the caller's
>> "return-to" address at the end of the called subroutine -
>
> That would require the caller to know the end of the subroutine.
>
> You are probably referring to the CDC. It would write a jump back
> to the caller at the *first* word of the callee and begin execution
> at the 2nd word.

I remember that from the days not so long ago when the UofMinn
used to torture students by making them program on a 6600.  I
always wondered how one did recursion or re-entrancy on a 6600,
but the professor who taught that class wasn't really up on
modern stuff like that.  He had also never heard of passing
parameters by value.

-- 
Grant Edwards                   grante             Yow!  YOW!! The land of the
                                  at               rising SONY!!
                               visi.com            

"Dick Wesseling" <free@securityaudit.val.newsbank.net> wrote
> "Nicholas O. Lindan" <see@sig.com> writes:
> >
> > by such subtle methods as writing a JMP instruction to the caller's
> > "return-to" address at the end of the called subroutine -
> 
> That would require the caller to know the end of the subroutine.
 
And?  The caller has to know the entry point, yah?  Knowing the
exit point is somehow interdict?

> You are probably referring to the CDC.

No, I am not.  Why, because as you so state:

> [A CDC mainframe] would write a jump back
> to the caller at the *first* word of the callee and begin execution
> at the 2nd word

This was an improvement, for modern day dilettantes.

-- 
Nicholas O. Lindan, Cleveland, Ohio
Consulting Engineer:  Electronics; Informatics; Photonics.
Remove spaces etc. to reply: n o lindan at net com dot com
psst.. want to buy an f-stop timer? nolindan.com/da/fstop/
.