Control loop precision

lasselangwadtchristensen@gmail.com writes:

> Den lørdag den 4. juni 2016 kl. 01.18.48 UTC+2 skrev Richard Damon:
>> On 6/3/16 4:18 PM, edward.ming.lee@gmail.com wrote:
>> > On Friday, June 3, 2016 at 10:38:02 AM UTC-7, alb wrote:
>> >> Hi Tim,
>> >>
>> >> On 03.06.2016 18:35, Tim Wescott wrote:
>> >>>> I have a current control loop based on a PI controller, a PWM and a
>> >>>> half-bridge to drive current through a phase of a BLDC. The current is
>> >>>> measured via an OPAMP and ADC and fed back to the PI.
>> >> []
>> >>>> Not only I have to calculate the output precision, but eventually I
>> >>>> should make sure that any single block of my control loop is correctly
>> >>>> sized in order to achieve my target without the need to over specify any
>> >>>> one in particular.
>> >> []
>> >>> I'm assuming that the PI controller is controlling the PWM.
>> >>
>> >> correct assumption and the PI output is over a 12 bit, while the PWM is
>> >> 9 bit due to PWM carrier and main clock onboard (f_pwm = 88 kHz, f_clk =
>> >> 40 MHz => only 450 periods available, minus some dead zone at the
>> >> extremities of the full ranges due to H-bridge MOS transition time).
>> >> Therefore whatever kind of precision I have at the level of the PI it is
>> >> screwed up by a factor 4 in the PWM and I'm not sure I can do anything
>> >> about it.
>> >>
>> >
>> > Then your overall precision is no better than 9 bits.  Perhaps you need a faster CPU.
>> >
>> 
>> Not necessarily. If the bandwidth of the motor is significantly lower 
>> than the PWM frequency (which it almost certainly is), then you can get 
>> some more bits by dithering the PWM value. After all, isn't the basis of 
>> PWM using a ONE bit signal to generate a much higher number of states. 
>> It helps to be smart in how you do the dithering, to keep the frequency 
>> component of the dither high.
>
> one way of doing it would be to use delta sigma modulation to noise shape 
> the quantization to 9 bit pwm

Lasse, you beat me to this. I was going to say that to shape the
spectrum of the dither noise you'd need to put feedback around the
quantization.
-- 
Randy Yates, DSP/Embedded Firmware Developer
Digital Signal Labs
http://www.digitalsignallabs.com

On Sat, 04 Jun 2016 19:27:44 -0400, Randy Yates wrote:

> lasselangwadtchristensen@gmail.com writes:
> 
>> Den lørdag den 4. juni 2016 kl. 01.18.48 UTC+2 skrev Richard Damon:
>>> On 6/3/16 4:18 PM, edward.ming.lee@gmail.com wrote:
>>> > On Friday, June 3, 2016 at 10:38:02 AM UTC-7, alb wrote:
>>> >> Hi Tim,
>>> >>
>>> >> On 03.06.2016 18:35, Tim Wescott wrote:
>>> >>>> I have a current control loop based on a PI controller, a PWM and
>>> >>>> a half-bridge to drive current through a phase of a BLDC. The
>>> >>>> current is measured via an OPAMP and ADC and fed back to the PI.
>>> >> []
>>> >>>> Not only I have to calculate the output precision, but eventually
>>> >>>> I should make sure that any single block of my control loop is
>>> >>>> correctly sized in order to achieve my target without the need to
>>> >>>> over specify any one in particular.
>>> >> []
>>> >>> I'm assuming that the PI controller is controlling the PWM.
>>> >>
>>> >> correct assumption and the PI output is over a 12 bit, while the
>>> >> PWM is 9 bit due to PWM carrier and main clock onboard (f_pwm = 88
>>> >> kHz, f_clk =
>>> >> 40 MHz => only 450 periods available, minus some dead zone at the
>>> >> extremities of the full ranges due to H-bridge MOS transition
>>> >> time). Therefore whatever kind of precision I have at the level of
>>> >> the PI it is screwed up by a factor 4 in the PWM and I'm not sure I
>>> >> can do anything about it.
>>> >>
>>> >>
>>> > Then your overall precision is no better than 9 bits.  Perhaps you
>>> > need a faster CPU.
>>> >
>>> >
>>> Not necessarily. If the bandwidth of the motor is significantly lower
>>> than the PWM frequency (which it almost certainly is), then you can
>>> get some more bits by dithering the PWM value. After all, isn't the
>>> basis of PWM using a ONE bit signal to generate a much higher number
>>> of states. It helps to be smart in how you do the dithering, to keep
>>> the frequency component of the dither high.
>>
>> one way of doing it would be to use delta sigma modulation to noise
>> shape the quantization to 9 bit pwm
> 
> Lasse, you beat me to this. I was going to say that to shape the
> spectrum of the dither noise you'd need to put feedback around the
> quantization.

Fully explained here -- at least up to a 1st-order sigma-delta.  I don't 
know more is necessarily better for most plants.

<http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta-
techniques-extend-DAC-resolution>

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

Hi Tim,

On 05.06.2016 01:55, Tim Wescott wrote:
[]
>>> one way of doing it would be to use delta sigma modulation to noise
>>> shape the quantization to 9 bit pwm
[]
> Fully explained here -- at least up to a 1st-order sigma-delta.  I don't 
> know more is necessarily better for most plants.
> 
> <http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta-
> techniques-extend-DAC-resolution>

We've had the same idea in our group. It's a tradeoff since the extra
delta-sigma implies additional resources that we do not easily get on a
small size FPGA, moreover we have three three-phases bldc motors to
drive and therefore 9 delta-sigmas may be quickly a resource hungry
solution.

Certainly if the system is left as is, the precision is driven by the 9
bits PWM. Since I believe the instantaneous precision is not what
matters most, the sigma-delta may be a viable solution.

Certainly increasing the system clock is not an option, a one bit
precision increase would mean going from 80 MHz to 160 MHz and I may
have side issues with time closure on the FPGA design, other than
potential implications in my radiated performances.

As a side question, what would be a good measurement setup for assessing
precision? How would I judge how many points I need to collect and at
which sampling rate? Should I then measure RMS? What kind of bandwidth
my measurement system should have? The higher harmonic content of the
PWM is certainly something I'm not particularly interested in, neither
is the customer since the motor has a strong low-pass filter behavior.

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Hi Edward,

On 03.06.2016 22:59, edward.ming.lee@gmail.com wrote:
[]
>> Typically the precision of the drive that's applied to a motor can
>> be far less than what you need at the motor shaft.  So I wouldn't
>> hold to this rule of thumb too tightly.
> 
> Yes, i know.  The current precision (which he asked) is 9 bits, but
> the speed precision (which people are interested in) could be far
> less.  The current to speed ratio can also depend on age.  However,
> higher current precision will certainly give better speed precision.
> 

Unfortunately I do not have many details on the position precision
required at system level since we are providing only the platform, while
the controller parameters are set by the customer. The controller is an
IIR with feed forward and a transfer function to convert torque into
current.

On the contrary, the current loop is designed in order to move the motor
pole far away from the signal band in order to avoid stability issues.

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Hi Tim,

On 05.06.2016 01:55, Tim Wescott wrote:
[]
>> Lasse, you beat me to this. I was going to say that to shape the
>> spectrum of the dither noise you'd need to put feedback around the
>> quantization.
> 
> Fully explained here -- at least up to a 1st-order sigma-delta.  I don't 
> know more is necessarily better for most plants.
> 
> <http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta-
> techniques-extend-DAC-resolution>

While the paper in general is quite clear on the advantage of the
sigma-delta, I didn't quite understand the examples, especially the
first one.

On the phase-locking system, why would you need a 10 or even 12-bit DAC?
I reckon that for 0.5 degree requirement a 200/512=0.39 degree would be
more than sufficient, therefore a 10-bit would suffice.

Secondly, how do you get to the 0.031 degrees/sample^2 with the
sigma-delta? I didn't quite get that.

-- 
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Den søndag den 5. juni 2016 kl. 11.36.14 UTC+2 skrev alb:
> Hi Tim,
> 
> On 05.06.2016 01:55, Tim Wescott wrote:
> []
> >>> one way of doing it would be to use delta sigma modulation to noise
> >>> shape the quantization to 9 bit pwm
> []
> > Fully explained here -- at least up to a 1st-order sigma-delta.  I don't 
> > know more is necessarily better for most plants.
> > 
> > <http://www.embedded.com/design/configurable-systems/4006431/Sigma-delta-
> > techniques-extend-DAC-resolution>
> 
> We've had the same idea in our group. It's a tradeoff since the extra
> delta-sigma implies additional resources that we do not easily get on a
> small size FPGA, moreover we have three three-phases bldc motors to
> drive and therefore 9 delta-sigmas may be quickly a resource hungry
> solution.

it is one register and an adder


-Lasse

Den søndag den 5. juni 2016 kl. 01.55.08 UTC+2 skrev Tim Wescott:
> On Sat, 04 Jun 2016 19:27:44 -0400, Randy Yates wrote:
> 
> > lasselangwadtchristensen@gmail.com writes:
> > 
> >> Den lørdag den 4. juni 2016 kl. 01.18.48 UTC+2 skrev Richard Damon:
> >>> On 6/3/16 4:18 PM, edward.ming.lee@gmail.com wrote:
> >>> > On Friday, June 3, 2016 at 10:38:02 AM UTC-7, alb wrote:
> >>> >> Hi Tim,
> >>> >>
> >>> >> On 03.06.2016 18:35, Tim Wescott wrote:
> >>> >>>> I have a current control loop based on a PI controller, a PWM and
> >>> >>>> a half-bridge to drive current through a phase of a BLDC. The
> >>> >>>> current is measured via an OPAMP and ADC and fed back to the PI.
> >>> >> []
> >>> >>>> Not only I have to calculate the output precision, but eventually
> >>> >>>> I should make sure that any single block of my control loop is
> >>> >>>> correctly sized in order to achieve my target without the need to
> >>> >>>> over specify any one in particular.
> >>> >> []
> >>> >>> I'm assuming that the PI controller is controlling the PWM.
> >>> >>
> >>> >> correct assumption and the PI output is over a 12 bit, while the
> >>> >> PWM is 9 bit due to PWM carrier and main clock onboard (f_pwm = 88
> >>> >> kHz, f_clk =
> >>> >> 40 MHz => only 450 periods available, minus some dead zone at the
> >>> >> extremities of the full ranges due to H-bridge MOS transition
> >>> >> time). Therefore whatever kind of precision I have at the level of
> >>> >> the PI it is screwed up by a factor 4 in the PWM and I'm not sure I
> >>> >> can do anything about it.
> >>> >>
> >>> >>
> >>> > Then your overall precision is no better than 9 bits.  Perhaps you
> >>> > need a faster CPU.
> >>> >
> >>> >
> >>> Not necessarily. If the bandwidth of the motor is significantly lower
> >>> than the PWM frequency (which it almost certainly is), then you can
> >>> get some more bits by dithering the PWM value. After all, isn't the
> >>> basis of PWM using a ONE bit signal to generate a much higher number
> >>> of states. It helps to be smart in how you do the dithering, to keep
> >>> the frequency component of the dither high.
> >>
> >> one way of doing it would be to use delta sigma modulation to noise
> >> shape the quantization to 9 bit pwm
> > 
> > Lasse, you beat me to this. I was going to say that to shape the
> > spectrum of the dither noise you'd need to put feedback around the
> > quantization.
> 
> Fully explained here -- at least up to a 1st-order sigma-delta.  I don't 
> know more is necessarily better for most plants.
> 

might be a good idea top stick to first order anyway, since it 
unconditionally stable

-Lasse

On 05.06.2016 21:56, lasselangwadtchristensen@gmail.com wrote:
[]
>> We've had the same idea in our group. It's a tradeoff since the extra
>> delta-sigma implies additional resources that we do not easily get on a
>> small size FPGA, moreover we have three three-phases bldc motors to
>> drive and therefore 9 delta-sigmas may be quickly a resource hungry
>> solution.
> 
> it is one register and an adder

Nothing is free in life! The register and adder would need to be
configured according to the limits for the range at minimum, meaning
additional control logic and parameters to store plus logic to max the
output. I can easily eat up few percents of my real estate, which is not
currently an issue, given the margins we have, but which may be one day.

We have already an arithmetic unit onboard, but is shared and accessed
through a central bus. Adding traffic on the bus just for the
sigma-delta would eat-up too much bandwidth. But I think that a local
adder won't hurt much.

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On Sun, 05 Jun 2016 11:36:10 +0200, alb wrote:

> Hi Tim,
> 
> On 05.06.2016 01:55, Tim Wescott wrote:
> []
>>>> one way of doing it would be to use delta sigma modulation to noise
>>>> shape the quantization to 9 bit pwm
> []
>> Fully explained here -- at least up to a 1st-order sigma-delta.  I
>> don't know more is necessarily better for most plants.
>> 
>> <http://www.embedded.com/design/configurable-systems/4006431/Sigma-
delta-
>> techniques-extend-DAC-resolution>
> 
> We've had the same idea in our group. It's a tradeoff since the extra
> delta-sigma implies additional resources that we do not easily get on a
> small size FPGA, moreover we have three three-phases bldc motors to
> drive and therefore 9 delta-sigmas may be quickly a resource hungry
> solution.
> 
> Certainly if the system is left as is, the precision is driven by the 9
> bits PWM. Since I believe the instantaneous precision is not what
> matters most, the sigma-delta may be a viable solution.
> 
> Certainly increasing the system clock is not an option, a one bit
> precision increase would mean going from 80 MHz to 160 MHz and I may
> have side issues with time closure on the FPGA design, other than
> potential implications in my radiated performances.
> 
> As a side question, what would be a good measurement setup for assessing
> precision? How would I judge how many points I need to collect and at
> which sampling rate? Should I then measure RMS? What kind of bandwidth
> my measurement system should have? The higher harmonic content of the
> PWM is certainly something I'm not particularly interested in, neither
> is the customer since the motor has a strong low-pass filter behavior.

Are you driving the PWM from software on a processor, or is it on the 
FPGA?

There should be plenty of time to implement that as the last block in a 
software-based control loop, assuming you need it at all.

If you can take a quick look at the PWM command you'll know -- if it's 
already bouncing all around from noise, then there's no need to add 
dither of your own.

-- 
Tim Wescott
Control systems, embedded software and circuit design
I'm looking for work!  See my website if you're interested
http://www.wescottdesign.com

On 06.06.2016 04:28, Tim Wescott wrote:
[]
> Are you driving the PWM from software on a processor, or is it on the 
> FPGA?

It's in the FPGA, no software allowed :-/. In some sectors of the space
industry software is still seen as a witchcraft and avoided at any cost,
at least in some types of application. I find it completely idiotic but
that's how it is.

[]
> If you can take a quick look at the PWM command you'll know -- if it's 
> already bouncing all around from noise, then there's no need to add 
> dither of your own.

The unfortunate thing is that we're only building the controller, while
the integration with the motor is performed on the customer site. On our
site we simulate the motors with passive loads and any effect related to
the motor is addressed by design (back-emf, dynamics, etc.).

But as Lasse mentioned it shouldn't be complicated to include a first
order delta-sigma. I'd try to model it first and see the effect.

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?