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Arm, gdb and jtag

Started by db January 11, 2004
Alaric B Snell wrote:
> > Ralph Malph wrote: > > >>So a dependency upon the Xilinx software :-( Which I bet they don't > >>provide a version of that will run on a Z80 to dynamically reconfigure > >>an IO glue FPGA, eh? :-) > > > If you are talking about using different bit streams, then you don't > > need anything special on the Z80 other than the code to bit bang the > > configuration data into the part. If you are talking about *changing* > > the bit stream in the Z80, then you are working on a very long and > > tedious project. > > I'd like to be able to generate my own bit stream. I'm not worried about > the requirements of compiling a logical specification to a description > of how the PLD should wire itself up, based upon the documentation of > the PLD's routing capabilities; I can do that, it's just that I can't > find documentation for how to generate the actual bit stream that will > make the PLD wire itself up as I wish. > > I've experimented with compiling hardware descriptions for my own design > of *simulated* PLD :-)
PLDs come in two flavors, simple and complex. There *are* specs for the simple PLDs because they consist of only the AND fuse array (AFAIK). All 16L8's use the same fuse map, for example. The complex CPLDs are all different. But if you are smart enough to write your own routing software, you should be clever enough to reverse engineer the parts from various downloads. This may be tedious, but it will work. The structures in a CPLD are very regular so that you only need to figure out a part of the device and you then have a much larger hunk. FPGAs are a whole new level of complexity. But again a lot of the device is very regular. But there is a lot more to the irregular part.
Ralph Malph wrote:

> PLDs come in two flavors, simple and complex. There *are* specs for the > simple PLDs because they consist of only the AND fuse array (AFAIK). > All 16L8's use the same fuse map, for example.
Aye.
> The complex CPLDs are all different. But if you are smart enough to > write your own routing software, you should be clever enough to reverse > engineer the parts from various downloads. This may be tedious, but it > will work.
You don't have to be very smart to write software to decide how to program a PLD unless you're doing what the development tools do and accepting arbitrary logic equations. Then you need to allocate logic to PALs (or across multiple PALs) within the device based on what macrocells need to be connected to what and the capacities of the PALs, but then in the PAL generation phase you may find enough common terms between equations in a given PAL that it has space left over so other bits of logic could be implemented there, saving interconnection matrix space... All textbook optimisation techniques, but tricky to develop due to a lot of details that need attention. My application would more be to hand-produce a number of 'macrocell' designs, and then at run time decide which 'macrocell' to put into each of a number of 'slots', and how to wire them to each other. Which is relatively trivial - just compose the bit streams for each macrocell to create the fuse maps for the PAL blocks, then work out an interconnect fuse map to tie them together. > The structures in a CPLD are very regular so that you only
> need to figure out a part of the device and you then have a much larger > hunk.
The ones I have lying around consist of four PALs with special I/O macrocells (that can be a range of flip flops, mainly) connected with an interconnect matrix to each other and the outputs of the chip. I reckon the four PAL blocks should be relatively easy to find in the fusemaps, particularly since I could probably isolate them by compiling designs with varying options for the macrocells to see where the macrocells are defined... but it would be much nicer to just get the programming documentation for the part :-)
> FPGAs are a whole new level of complexity. But again a lot of the > device is very regular. But there is a lot more to the irregular part.
Yes! ABS

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