Source for SDRAM chips

On Tue, 28 Dec 2004 13:41:55 -0800, larwe wrote:

> Sorry, programmable logic is not my specialty, but I second Richard in
> the belief that you likely can't do it in a CPLD. It's complicated.

I did a SDRAM controller for an AD 2185 DSP and a 1Mx16 SDRAM
in a xilinx 95108 along with some clock generation and DAC
interface logic some while back.  IIRC the cpu handled refresh,
the sdram was run at 33 Mhz cas latency 1.