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Memfault Beyond the Launch

Does ARMs support bytes?

Started by Elder Costa March 8, 2005
Ulf Samuelsson wrote:

> "Jim Granville" <no.spam@designtools.co.nz> skrev i meddelandet > news:42309577$1@clear.net.nz... > >>Joseph wrote: >> >>>The new Cortex cores will provide better code density >>>and performance from the Thumb-2 instruction set. >>>For more details see >>>http://www.arm.com/products/CPUs/ARM_Cortex-M3.html >>>and >>>http://www.arm.com/products/CPUs/archi-thumb2.html >> >> Are there any opcode level details on Cortex yet ? - the >>links above are large on 'warm fuzzies' and small on real info.. >> >>-jg > > > Question is how successful the Cortex cores will be over time. > > Should anyone in the semiconductor industry be interested in paying money > for an ARM Ltd core which is not an ARM? > I mean compared to lets say the MIPS, Tricore, PowerPC, Coldfire or > whatever. > The value of the Cortex is much lower than that of the ARM > Anyone can build a better core than the ARM, but you wont get access to the > tools/customer base > unless you do a lot of things right. > The AVR team has managed to introduce a new architecture which became > popular, > The consisten flash approach helped, like the OTP did help the PIC. > but it is harder in the high end. You need O/S. > It is possible to introduce new cores if you know how, but look how Motorola > failed with the M-Core. > They have some success with Coldfire where the price has dropped, but as > long as you > meet the pricing, people go ARM. > > Should anyone in the tools business be interested? No customers yet. > Before anyone releases a general purpose micro, there wont be enough market > to finance tools > unless ARM pays up, but I think they rather sell their own compiler. > > It will certainly be of some academic interest.
Yes, all good points, which is why seeing opcode and binary details are important. The Cortex is not ARM7 binary compatible, but may have enough commonality that porting tools is not a big issue. Right now, ARM seem to be very short on public release of the important details. I can understand that those with a big investment in ARM7 might be a little concerned by this. -jg
On Thu, 10 Mar 2005 20:19:40 -0000, Vadim Borshchev
<vadim.borshchev@127.0.0.1> wrote:

>On Thu, 10 Mar 2005 07:07:48 +0000 (UTC), Wim Lewis <wiml@hhhh.org> wrote: > >>> char buffer[16]; > >> It'll occupy 16 8-bit bytes (or 4 32-bit words), but it's possible >> that a statement such as >> >> buffer[3] = x; >> >> will end up reading the 32-bit word containing that byte, modifying >> the word, and then writing it back. > >ARM has instructions to load bytes (with or without sign extension) and >store bytes. IME I have never come across a compiler doing this.
I believe it is possible for a hardware memory interface to do this "behind your back," i.e., even though the assembly loads and stores a byte, larger chunks of memory may be read, modified and written back by the memory interface hardware. I don't know if any ARM chip will do this, and it's really only critical to know about it in shared memory situations... Regards, -=Dave -- Change is inevitable, progress is not.
Jim Granville wrote:
> Joseph wrote: > >> The new Cortex cores will provide better code density >> and performance from the Thumb-2 instruction set. >> For more details see >> http://www.arm.com/products/CPUs/ARM_Cortex-M3.html >> and >> http://www.arm.com/products/CPUs/archi-thumb2.html > > > Are there any opcode level details on Cortex yet ? - the > links above are large on 'warm fuzzies' and small on real info.. > > -jg >
Hi Jim, No, sorry. The opcode level details are not release on public domain yet. regards, Joseph This e-mail message is intended for the addressee(s) only and may contain information that is the property of, and/or subject to a confidentiality agreement between the intended recipient(s), their organisation and/or the ARM Group of Companies. If you are not an intended recipient of this e-mail message, you should not read, copy, forward or otherwise distribute or further disclose the information in it; misuse of the contents of this e-mail message may violate various laws in your state, country or jurisdiction. If you have received this e-mail message in error, please contact the originator of this e-mail message via e-mail and delete all copies of this message from your computer or network, thank you.
Joseph wrote:
> > Hi Jim, > > No, sorry. The opcode level details are not release on public > domain yet. > > regards, > Joseph >
Sorry for replying to my own post. It seems it has just been released to customer with NDA (non-disclosure agreement). See http://www.arm.com/news/8513.html Joseph This e-mail message is intended for the addressee(s) only and may contain information that is the property of, and/or subject to a confidentiality agreement between the intended recipient(s), their organisation and/or the ARM Group of Companies. If you are not an intended recipient of this e-mail message, you should not read, copy, forward or otherwise distribute or further disclose the information in it; misuse of the contents of this e-mail message may violate various laws in your state, country or jurisdiction. If you have received this e-mail message in error, please contact the originator of this e-mail message via e-mail and delete all copies of this message from your computer or network, thank you.
Joseph wrote:
> Joseph wrote: >> >> No, sorry. The opcode level details are not release on public >> domain yet. > > Sorry for replying to my own post. > It seems it has just been released to customer with NDA > (non-disclosure agreement). See > http://www.arm.com/news/8513.html
Am I missing something, or is this the height of stupidity. We are selling a processor, but you can't know what's in the instruction set? The time to promulgate that is before the design is complete, in order to get comments from the general public. -- Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net> USE worldnet address!
CBFalconer wrote:
> Joseph wrote: > >>Joseph wrote: >> >>>No, sorry. The opcode level details are not release on public >>>domain yet. >> >>Sorry for replying to my own post. >>It seems it has just been released to customer with NDA >>(non-disclosure agreement). See >>http://www.arm.com/news/8513.html > > > Am I missing something, or is this the height of stupidity. We are > selling a processor, but you can't know what's in the instruction > set? The time to promulgate that is before the design is complete, > in order to get comments from the general public.
Close to stupidity, but a sad sign of what happens when lawyers out-number engineers in a company.... It means we are expected to believe their marketing hoopla, but cannot actually verify any of the claims. -jg
CBFalconer wrote:
> Joseph wrote: > >>Joseph wrote: >> >>>No, sorry. The opcode level details are not release on public >>>domain yet. >> >>Sorry for replying to my own post. >>It seems it has just been released to customer with NDA >>(non-disclosure agreement). See >>http://www.arm.com/news/8513.html > > > Am I missing something, or is this the height of stupidity. We are > selling a processor, but you can't know what's in the instruction > set? The time to promulgate that is before the design is complete, > in order to get comments from the general public. >
Hi guys, Don't worry. The instruction details will be released to public, it just take time to finish off all the documentation works! :-) Bear in mind once the design is released to silicon partners, it will take another several months (or even half year) for them to produce the actual silicon chips. (Honestly I don't know how much of the paper works are in the legal department ;-) ) Joseph This e-mail message is intended for the addressee(s) only and may contain information that is the property of, and/or subject to a confidentiality agreement between the intended recipient(s), their organisation and/or the ARM Group of Companies. If you are not an intended recipient of this e-mail message, you should not read, copy, forward or otherwise distribute or further disclose the information in it; misuse of the contents of this e-mail message may violate various laws in your state, country or jurisdiction. If you have received this e-mail message in error, please contact the originator of this e-mail message via e-mail and delete all copies of this message from your computer or network, thank you.
Joseph wrote:
> CBFalconer wrote: >> Joseph wrote: >>> Joseph wrote: >>> >>>> No, sorry. The opcode level details are not release on public >>>> domain yet. >>> >>> Sorry for replying to my own post. >>> It seems it has just been released to customer with NDA >>> (non-disclosure agreement). See >>> http://www.arm.com/news/8513.html >> >> Am I missing something, or is this the height of stupidity. We are >> selling a processor, but you can't know what's in the instruction >> set? The time to promulgate that is before the design is complete, >> in order to get comments from the general public. > > Don't worry. The instruction details will be released to public, it > just take time to finish off all the documentation works! :-) > > Bear in mind once the design is released to silicon partners, it > will take another several months (or even half year) for them to > produce the actual silicon chips. > > (Honestly I don't know how much of the paper works are in the legal > department ;-) )
The answer appears to be "Yes, the height of stupidity. We are not capable of marking any early release documents as 'Preliminary, subject to change'". This is purely an academic comment on my part. -- "If you want to post a followup via groups.google.com, don't use the broken "Reply" link at the bottom of the article. Click on "show options" at the top of the article, then click on the "Reply" at the bottom of the article headers." - Keith Thompson
Hi there,

The "early access" architecture specification has been released quite a 
long time ago (e.g. to ARM partners and development tools vendors). The 
one on 7 March is an official release.  If you read the details of the 
press release, you will see some development tools vendors has been 
working with the V7 architecture already. 
(http://www.arm.com/news/8513.html)

In the following link, you can find some of the details about the V7 
architecture and Thumb-2 instruction set. (see bottom of the page)
http://www.arm.com/products/CPUs/architecture.html

Joseph

This e-mail message is intended for the addressee(s) only
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recipient(s), their organisation and/or the ARM Group of
Companies. If you are not an intended recipient of this
e-mail message, you should not read, copy, forward or
otherwise distribute or further disclose the information
in it; misuse of the contents of this e-mail message may
violate various laws in your state, country or jurisdiction.
If you have received this e-mail message in error, please
contact the originator of this e-mail message via e-mail
and delete all copies of this message from your computer
or network, thank you.
Joseph wrote:
> > Hi there, > > The "early access" architecture specification has been released quite a > long time ago (e.g. to ARM partners and development tools vendors). The > one on 7 March is an official release. If you read the details of the > press release, you will see some development tools vendors has been > working with the V7 architecture already. > (http://www.arm.com/news/8513.html) > > In the following link, you can find some of the details about the V7 > architecture and Thumb-2 instruction set. (see bottom of the page) > http://www.arm.com/products/CPUs/architecture.html
thanks Joseph, A quick scan of this info, shows : * Thumb-2 is not binary compatible with Thumb[16] or ARM[32] * Thumb-2 removes the need to juggle/optimise your app for Size.Speed across the 16 and 32 bit opcode alternatives. * Thumb-2 introduces (among other things) variable length opcodes, and atomic Bit access. * Thumb-2 also adds opcodes for 16 bit constant load, short skips [IF THEN], bit fields, bit reversal, TestZ&Branch, TableBranch, improved interrupt handling (HW Stacking)..... They state all this gives you a 5% smaller and 2-3% faster code than Thumb. [presumably those values are averages, maybe even 'marketing-filtered' averages :) ? ] Variable length opcodes, atomic Bit access, TestZ&Branch will be very familiar to 80C51 users. Thus yes, Cortex will be a better MicroController core than earlier ARMs. Comment: There is likely to be some confusion in the field, between ARMv7, and ARM7. Reminds me of the Philips XA51, where Philips tried to coat-tail on the large 80C51 market, with a device that was NOT binary compatible. Time will tell how Cortex flies. <paste> Joseph wrote:
> Hi guys, > > Don't worry. The instruction details will be released to public, it just take time to finish off all the documentation works! > > Bear in mind once the design is released to silicon partners, it will take another several months (or even half year) for them to produce the actual silicon chips.
Hmmm, well one of those papers is dated June 2003, and the Opcodes are defined very early in a processor design. Releasing opcode info is also just a simple text file, so consumes very little actual publishing effort. Of course the silicon follows some time later, but designers can decide what to place on their radar much earlier in a life cycle. -jg

Memfault Beyond the Launch