Flash write issue

Thad Smith wrote:
> Meindert Sprang wrote:
> > "Thad Smith" <ThadSmith@acm.org> wrote in message
> > news:4305dc6e$0$79779$892e0abb@auth.newsreader.octanews.com...
> >
> >>linnix wrote:

First of all, it depends on whether we are talking about NAND or NOR
flash.  NOR flash is like static ram, which is cell addressable.  NAND
flash is like dynamic ram, which is row & col addressable.  In fact,
for most NAND flash devices (CF,SD,etc), you can't even deal with the
flash directly.  You send a block of data to the on-board controller,
it may or may not rewrite the block in the same space.  Depending on
the implementation, it might even be advantageous to write to a new
block every time.  This would spread out the cell wearing.
Unfortunately, writing a bit would cause an entire block of writing.

> >>
> >>>Thad Smith wrote:
> >>>
> >>>>"sailor.gu@gmail.com" wrote:
> >>>>
> >>>>>1. As you said, change 1s to 0s need not erase, so it is not a
> >>>>>write/erase cycle, right?
> >>>>
> >>>>Correct, it is only a write.  No erasure is done.

You can't control it with NAND flash.

> >>>
> >>>Flash memories are rated 100,000 write cycles, not just erase cycles.
> >>
> >>Interesting.  Does that mean that using page writes provides N times
> >>less wear than single byte writes, where both modes are available and N
> >>is the size of the page?
> >
> > No. The 100,000 cycles are per cell/bit. Since you can only change a 1 to 0
> > once and then erase it, that counts as one cycle. Filling a page byte by
> > byte, with separate write cycles, or doing a page write makes no difference
> > for each cell, they only get changed from 1 to 0 once. When you erase the
> > entire page, all cells change to 1 again so the write/erase cycle is
> > complete. So it's safe to say that 100,000 write cycles is the same as
> > 100,000 page erase cycles.
>
> That's what I thought, but linnix wrote:
> >
> > Depends on how the flash is built.  Rather than addressing individual
> > cells.  Flash controller addresses a block of cells.  There are much
> > less write amplifiers vs. cells.  You can think of DRAM's row & col
> > addressing.  Turning on a row will wear out all the cells sharing the
> > row.

By sharing addressing and refleshing logics, NAND are cheaper to build
than NOR.  Each cell is like a tiny battery.  Unfortunately, battery
don't last forever, since charging is also weakening the holding
capabiblity.

If I can borrow 5 billion yuan, I would do it differently.  I would
build separate batteries at the charger level.  This would shorten the
holding time between chargings, but also remove the write cycle
limitation.  The down size is that you have to power it up at least
once in a while.  The up size is that you can use it like a hard disk.

>
> That would argue for page writes, assuming that wrote a single "row" at
> once, as wearing less that individual byte writes.
>
> So the question becomes what is a write cycle for a single cell, as far
> as wearout goes: writing that particular cell or writing any cell on the
> same "row"?
> 
> Thad

"linnix" <me@linnix.info-for.us> wrote in message
news:1124718852.726530.213940@g43g2000cwa.googlegroups.com...
> First of all, it depends on whether we are talking about NAND or NOR
> flash.  NOR flash is like static ram, which is cell addressable.  NAND
> flash is like dynamic ram, which is row & col addressable.  In fact,
> for most NAND flash devices (CF,SD,etc), you can't even deal with the
> flash directly.  You send a block of data to the on-board controller,
> it may or may not rewrite the block in the same space.  Depending on
> the implementation, it might even be advantageous to write to a new
> block every time.  This would spread out the cell wearing.
> Unfortunately, writing a bit would cause an entire block of writing.

I was referring to normal flash chips, like Am29F010 and the like. I don't
know if these are NAND or NOR flash, but the datasheet shows a matrix, but
they're all byte addressable and they write a single byte at a time. Similar
flashes from Atmel however, do write a page at a time (256 bytes, for
instance). These are all "normal" chips with an address and databus
(parallel).

Meindert