What am I doing wrong?

On 2005-10-03, Keyser Soze <noreturn@nothere.com> wrote:
> We have not told you one of the really sneaky bit of the interrupt handling 
> on the PIC processors.
>
> There are two global interrupt enable bits.
>
> One bit is the GIE bit in the INTCON register, bit 7.
>
> The other is buried inside the PIC with no direct access from the program.
>
> This bit is "set" when the RETFIE is executed and "cleared" when any 
> interrupt is processed.
>
> For an interrupt to occur at least one interrupt source must be enabled, the 
> GIE bit in INTCON must be set to one and the internal global interrupt 
> enable must be "set". If the interrupt source is one of the peripheral 
> device then the PEIE bit in INTCON must also be set to one.

There is no "internal global interrupt enable bit."

-- 
John W. Temples, III

"John Temples" <usenet@xargs-spam.com> wrote in message news:slrndk2ltf.akt.usenet@jwt.xargs.com...
> On 2005-10-03, Keyser Soze <noreturn@nothere.com> wrote:
> > We have not told you one of the really sneaky bit of the interrupt handling
> > on the PIC processors.
> >
> > There are two global interrupt enable bits.
> >
> > One bit is the GIE bit in the INTCON register, bit 7.
> >
> > The other is buried inside the PIC with no direct access from the program.
> >
> > This bit is "set" when the RETFIE is executed and "cleared" when any
> > interrupt is processed.
> >
> > For an interrupt to occur at least one interrupt source must be enabled, the
> > GIE bit in INTCON must be set to one and the internal global interrupt
> > enable must be "set". If the interrupt source is one of the peripheral
> > device then the PEIE bit in INTCON must also be set to one.
>
> There is no "internal global interrupt enable bit."
>
Oh my, you are of course correct.

Although I seem to remember an errata for one of the first 16Cxx
parts to implement interrupt may have had some such quirk.

Sorry for the missinformation.

On 2005-10-03, Keyser Soze <noreturn@nothere.com> wrote:
> "John Temples" <usenet@xargs-spam.com> wrote in message news:slrndk2ltf.akt.usenet@jwt.xargs.com...
>> There is no "internal global interrupt enable bit."
>>
> Oh my, you are of course correct.
>
> Although I seem to remember an errata for one of the first 16Cxx
> parts to implement interrupt may have had some such quirk.

There was an errata in the old 16Cs that if an interrupt occurred
in the same instruction in which you were clearing GIE, GIE would not
clear; you had to test GIE after clearing it to see that it actually
cleared.  Perhaps this is what you're thinking of.

-- 
John W. Temples, III

"John Temples" <usenet@xargs-spam.com> wrote in message 
news:slrndk3hmh.c0u.usenet@jwt.xargs.com...
> On 2005-10-03, Keyser Soze <noreturn@nothere.com> wrote:
>> "John Temples" <usenet@xargs-spam.com> wrote in message 
>> news:slrndk2ltf.akt.usenet@jwt.xargs.com...
>>> There is no "internal global interrupt enable bit."
>>>
>> Oh my, you are of course correct.
>>
>> Although I seem to remember an errata for one of the first 16Cxx
>> parts to implement interrupt may have had some such quirk.
>
> There was an errata in the old 16Cs that if an interrupt occurred
> in the same instruction in which you were clearing GIE, GIE would not
> clear; you had to test GIE after clearing it to see that it actually
> cleared.  Perhaps this is what you're thinking of.
>
No I don't think that was it.

It's more likely one of the "features" of the 8051.

I've been doing a few of those lately and the mix-master I'm using for a 
brain probably got confused again.