CPLD + SRAM == Cheap BiDir FIFO (albiet... slow)

Does anybody have a link to VHDL code to transform say...  XC9572 &
CY7C1399 into a 'slow' Dual 16Kx8 FIFO (for about $3.65 in Qty 100)

IDT's stuff is too $$$$ and I don't really need the 'instantaneous'
simultaneous access from "both sides"... handshaking with ready/done deal
is good enough.

On Sun, 09 Oct 2005 23:58:20 -0400, "jyaron" <mb1@yashu.com> wrote:

>Does anybody have a link to VHDL code to transform say...  XC9572 &
>CY7C1399 into a 'slow' Dual 16Kx8 FIFO (for about $3.65 in Qty 100)
>
>IDT's stuff is too $$$$ and I don't really need the 'instantaneous'
>simultaneous access from "both sides"... handshaking with ready/done deal
>is good enough.

Xilinx has quite a few app notes on FIFOs. This
http://direct.xilinx.com/bvdocs/appnotes/xapp175.pdf might be adaptable
to what you're trying to do.

-- 
Rich Webb   Norfolk, VA