AT91RM9200 and 16-bit SDRAM not working

In comp.arch.embedded,
Frieder Ferlemann <F.Ferlemann@identecsolutions.de> wrote:
>Stef wrote:
>> I have solid power planes (ground and 3V3) on the entire board and every
>> power pin of the SDRAM is bypassed with a 100nF capacitor. So I'm OK on
>
>Actually you might be better off with smaller capacitors.
>Check the impedance over frequency characteristics of the
>capacitors you are using.
>
That might be true, but unfortunately I can not find this information in 
the datasheet. I'm using samsung X7R 50V 0805 MLCC caps (CL21B104KBNC).

At the moment however, lowering the frequency does not seem to change a
thing and I am therefore now focussing on software problems, but I'll 
keep your suggestion in mind. If you look at the AT91RM9200 eval kit
schematics, you'll find they also use 100nF caps.

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

The first sign of maturity is the discovery that the volume knob also turns to 
the left.

In comp.arch.embedded,
Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid> wrote:
>In comp.arch.embedded,
>Karl Olsen <kro@nospam.post3.tele.dk> wrote:
>>In news:81548$4354fbb0$54f63171$17603@publishnet.news-service.com,
>>Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid> typed:
>
>>> pRegister = (int *)0xFFFFFF90; // SDRAMC_MR
>>> *pRegister = 0x00000013; // 16-bit, Load mode register on access
>>> pRegister = (int *)0x20000040;  // Address will go in mode reg. mode
>>> must be 0x020 *pRegister = 0;
>>>
>>Are you sure you load the mode register correctly?  In my AT91RM9200 with
>>32-bit SDRAM, I want to load the SDRAM mode register with 0x0020, and since
>>CPU A2-11 --> SDRAM A0-9, I use address 0x0080 on the CPU pins.  It works.
>>
>Reasonably sure, I verified with a scope that A5 is high during the load
>mode register command. But I will check this again.
>
This is geting weird:
I've tried different values and 0x20000010 lets A5 (SDRAM, A7 CPU) low as
expected. but ..20, ..40 and ..80 all put A5 high and A4/A6 low (other
address lines not connected to analyzer).

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Appendix:
	A portion of a book, for which nobody yet has discovered any use.

In comp.arch.embedded,
Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid> wrote:

[SDRAM problem]

Well the problem is solved! 32MB of SDRAM running happily at 73MHz.

It was, as always, a very silly mistake:
The pin numbers of RAS and CAS on the SDRAM's schematic symbol where
swapped. An error me and a collegue have overlooked several times. :-(((

The strangeness of A4=0,A5=1,A6=0 whether i write 0x020, 0x040 or 0x080
to the mode register remains. Maybe it's Atmel's way of enforcing a CAS
latency of 2 (the only value supported by the AT91RM9200)?

Now I still have a problem getting PLLA to work, but that's a different
thread. ;-)

Thank you all for thinking with me, it helped!

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Practical politics consists in ignoring facts.
		-- Henry Adams

>
> It was, as always, a very silly mistake:
> The pin numbers of RAS and CAS on the SDRAM's schematic symbol where
> swapped. An error me and a collegue have overlooked several times. :-(((
>

For which you and a colleague should get shot several times !

--
Cecil