OV7620 image sensor interface with FPGA headache

On Friday, in article
     <5d58f5b0e9550fb5ac711ef501869bfd@localhost.talkaboutelectronicequipment.com>
     dwmunandar@yahoo.com "dalle002" wrote:

>Hello again,
>
>Thanks to your input, the I2C register has been written succesfully!
>
>The next question is: Does anyone have output the digital signal to a VGA
>monitor successfully? I am assuming that today's computer monitor is
>progressive and should run at a minimum of 50Hz. But when the camera is in
>progressive mode, the VSYNC signal is only at 30Hz. I tried to lower the
>resolution to QVGA but still got 30Hz in progressive mode. The 30Hz signal
>cannot be displayed succesfully if sent directly to the monitor. I used
>only the HSYNC and VSYNC signal from the camera and use the FPGA to do a
>counting to provide the RGB signal output, but the monitor is blank even
>thought the pilot LED sense an incoming signal(the LED on the monitor that
>turns orange when there is no signal and turns green when the computer is
>running). Any suggestion for solving the problem without using a memory
>module?

See my other post.

The light on the front of the monitor only indicates that it has detected
a sync signal, not if it is valid or not.

Try setting the camera to colour bar test pattern output
(Reg 12 Common Control A bit 1), via the I2C to avoid other errors
look at the pattern coming out of the chip.

Get the registers set correctly for VGA interlaced 30fps, and use the
FPGA and some timing changes to output the faster timing and repeat
each line as a start. This is minimal memory requirements and two
line FIFOs should be possible inside a FPGA. Understand fully the
timing patterns you have to create to drive a monitor as VGA progressive
scan mode at 60FPS.

Clock the camera from the FPGA at 25MHz and use the 50MHz FPGA clock
to derive the output timing.

Consult some good books on video like (if still available)

        Video Demystified - A Handbook for the Digital Engineer
           By Keith Jack of Brooktree (when they made interesting chips)

        ISBN    1-878707-09-4

        See the November issue of Circuit Cellar for a VGA controller design
                <http://www.circuitcellar.com/

The amount of cirucitry (even inside an FPGA) is too much to describe
in enough details here, and is the sort of systems I have been working
on for years. Digital Video Processing in Real Time by hardware is not
simple and its intricacies have to be appreciated.

If I was doing much more than above for you, I would be doing the design
for you and putting myself out of business :-^

-- 
Paul Carpenter          | paul@pcserviceselectronics.co.uk
<http://www.pcserviceselectronics.co.uk/>    PC Services
<http://www.gnuh8.org.uk/>              GNU H8 & mailing list info
<http://www.badweb.org.uk/>             For those web sites you hate

Hello,

Thanks again for all your help. It has been very helpful. I have
successfully display the image from the camera onto the VGA monitor
according to Paul's suggestion by deinterlacing. Wohooo! Thank you so
much!

I took out the crystal oscillator off the camera board and use the FPGA to
clock the camera at 25MHz. The camera is run at RGB Interlaced mode. Then
I used the camera's VSYNC signal directly to the monitor but the FPGA is
the one that generates the HSYNC signal to the monitor for 480 lines. In
interlaced mode, the camera only gives 240 lines per field. Each line the
camera output is put in registers and sent to the monitor twice to
deinterlace it.
It works fine!

Thanks again for all the help.

On Monday, in article
     <6e966ad828e948d173eaeabafc14fc0c@localhost.talkaboutelectronicequipment.com>
     dwmunandar@yahoo.com "dalle002" wrote:

>Hello,
>
>Thanks again for all your help. It has been very helpful. I have
>successfully display the image from the camera onto the VGA monitor
>according to Paul's suggestion by deinterlacing. Wohooo! Thank you so
>much!

Glad it worked out for you.

>I took out the crystal oscillator off the camera board and use the FPGA to
>clock the camera at 25MHz. The camera is run at RGB Interlaced mode. Then
>I used the camera's VSYNC signal directly to the monitor but the FPGA is
>the one that generates the HSYNC signal to the monitor for 480 lines. In
>interlaced mode, the camera only gives 240 lines per field. Each line the
>camera output is put in registers and sent to the monitor twice to
>deinterlace it.

This has been the start of a long road of understanding video...

>It works fine!
>
>Thanks again for all the help.

Good to see a plan come together...

-- 
Paul Carpenter          | paul@pcserviceselectronics.co.uk
<http://www.pcserviceselectronics.co.uk/>    PC Services
<http://www.gnuh8.org.uk/>              GNU H8 & mailing list info
<http://www.badweb.org.uk/>             For those web sites you hate