Memory map?

Hi,

What is memory mapping. If i memory mapped registers in my pheipheral,.
The value written to them is teh value written to memory or it will be
written on physical registers in Pheripheral. Let me explain you cauz i
know my description is bit confusing.....

I have FPGA with a processor. Now i want to connect this processor with
Custom IP (on FPGA) using Processor Local Bus. I know custom IP has
bunch of registers which will recive the data and send the data. These
register i will create and to my understanding they are in pheripheral.
My question is ......

Are these registers really physically there or they are just the map.
SO when Processor will want to write to one of them it will write to
the memory and Pheripheral will knwo something is written to it?

"Fizzy" <fpgalearner@gmail.com> wrote in message 
news:1146236764.517924.301860@g10g2000cwb.googlegroups.com...
> Hi,
>
> What is memory mapping. If i memory mapped registers in my pheipheral,.
> The value written to them is teh value written to memory or it will be
> written on physical registers in Pheripheral. Let me explain you cauz i
> know my description is bit confusing.....

I'm not sure I completely understand your problem but I know what a memory 
map is and perhaps that will help you.

Suppose we have a processor with a 16bit address bus and an 8 bit data bus. 
This means you can directly address 2^16 locations - 65536 (10000hex) and 
therefore you can have a maximum of 64K of memory. Now let's say you have 8K 
of RAM and 8K of ROM. You would like to have it so that the first 8K memory 
location are RAM and the next 8K are ROM. You will need address decode logic 
to do this (in this case the top address bit connected to both device's chip 
selects will do).

This means your memory map will look like this (using hexadecimal numbers):
0000 ------------
               RAM
7FFF------------
8000-------------
               ROM
FFFF-------------

Now it doesn't have to be memory devices that you use - peripherals will 
work just as well. You could have a UART with 16 directly addressable 
registers. You could position it after the RAM and before the ROM (but it 
would mean 16 locations of ROM have to be sacrificed because you can only 
address 64K overall).

0000 ------------
               RAM
7FFF------------
8000-------------
               UART
800F-------------
8010-------------
               ROM
FFFF-------------

The UART does not know that it's address actually begins at 0x8000 - you 
will be required to have some logic which looks at the requested address on 
the address bus and decides that that address falls within the range of the 
UART and so the appropriate control signals to the UART should be asserted 
to access it. This is made simpler in an FPGA because you have plenty of 
logic available to do this.

> I have FPGA with a processor. Now i want to connect this processor with
> Custom IP (on FPGA) using Processor Local Bus. I know custom IP has
> bunch of registers which will recive the data and send the data. These
> register i will create and to my understanding they are in pheripheral.
> My question is ......
>
> Are these registers really physically there or they are just the map.
> SO when Processor will want to write to one of them it will write to
> the memory and Pheripheral will knwo something is written to it?
>

I'm not sure but I think your problem is in directing the processor to your 
registers. The processor will have its own idea of how it's memory map is 
laid out and you need to fit in around that. If, when you run your program 
and it wants to read from one of your custom IP registers, you need to make 
sure that your address decode logic provides that register's contents on the 
data bus when this address is requested. How that happens is up to you but 
if you put some thought into where in the processor's addressable memory 
space you want it to be it should be some fairly simple logic expression.

I'm not sure about what you mean with "Are these registers really physically 
there or they are just the map" but I think that they must be physically 
there but you get to them by accessing their place in the map. I.E. on my 
processor the first location in flash is at 0x44000000. If I read from that 
then the address decode logic knows I want to access flash and will wiggle 
the appropriate lines to get the flash to return its first word of data 
(address 0x00000000 according to the flash). 

Fizzy wrote:

> Hi,
> 
> What is memory mapping. 

Memory mapping is the design practice of making something look like 
memory (RAM, to be precise) to a processor.  You design your hardware so 
a write to a particular memory location causes a write to the peripheral 
in question, and a read from the memory location causes a read from the 
peripheral.

> If i memory mapped registers in my pheipheral,.
> The value written to them is teh value written to memory or it will be
> written on physical registers in Pheripheral.

You don't actually have memory at the peripheral location.  Just the 
peripheral.

Exactly what the peripheral does with a read or write command is up to 
the peripheral, but writes almost always go to a register (possibly 
short-lived if it's a transmit buffer in a communications interface like 
a UART).

> Let me explain you cauz i
> know my description is bit confusing.....
> 
> I have FPGA with a processor. Now i want to connect this processor with
> Custom IP (on FPGA) using Processor Local Bus. I know custom IP has
> bunch of registers which will recive the data and send the data. These
> register i will create and to my understanding they are in pheripheral.
> My question is ......
> 
> Are these registers really physically there or they are just the map.
> SO when Processor will want to write to one of them it will write to
> the memory and Pheripheral will knwo something is written to it?
> 
I general, yes the registers are physically there.  The processor will 
write to what it thinks is memory, the peripheral will get the message.


-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

If you have an address space that is larger than the amount of
memory you are going to use then you use some address bits
or combinations of them to select io connections.

If you have a small address space and it is filled with memory
you have to disable the memory access circuits in addition
to enable your io on the addresses you use. If you used a 3-and
of address bit-15, address bit-1 and address bit-0 you would
get a true when addressing only addresses where those
bits were true. If you have only 32K or less of memory then
access to address 8003h would enable the io device connected.
In fact if you only used 3 bits in your decoder any address
above 8000h that had bits 0 and 1 true would select this
device, 8003, 8007, 800B, 800F, ... FFF3, FFF7, FFFB, FFFF
If you only needed two io devices you could use two bits,
if you needed 32 registers you would need to decode 6 bits
in your io device select circuit etc.

One advantage of using a memory mapped io design is that
you will use the regular memory access instructions and you
won't need any special or restricted 'port' access opcodes
to complicate things.