DMA in UART .

Started by Sikandar July 17, 2006
HI,

I am using 16550 compatible UART. While this UART supports max speed of
about 11.5 Kbps which is connected to a V92 dialup  modem supporting
speeds upto 64Kbps .

I want to know the logic behind using  DMA inside the UART for
transmission to the FIFOs
Is this really required for such low speeds .


Regards in anticipation of replies,
Sikandar

On 2006-07-17, Sikandar <sikandar032@gmail.com> wrote:

> I am using 16550 compatible UART. While this UART supports max > speed of about 11.5 Kbps which is connected to a V92 dialup > modem supporting speeds upto 64Kbps. > > I want to know the logic behind using DMA inside the UART for > transmission to the FIFOs Is this really required for such low > speeds.
There is no DMA inside 16550 UARTs. -- Grant Edwards grante Yow! I'm into SOFTWARE! at visi.com
Grant Edwards wrote:
> On 2006-07-17, Sikandar <sikandar032@gmail.com> wrote: > > > I am using 16550 compatible UART. While this UART supports max > > speed of about 11.5 Kbps which is connected to a V92 dialup > > modem supporting speeds upto 64Kbps. > > > > I want to know the logic behind using DMA inside the UART for > > transmission to the FIFOs Is this really required for such low > > speeds. > > There is no DMA inside 16550 UARTs. > > -- > Grant Edwards grante Yow! I'm into SOFTWARE! > at > visi.com
There is a _highly_ misnamed DMA mode 1 and 2 in 16550 compliant UARTS, which really refers to their FIFO buffering mode. This is DMA in the sense the core has direct access to some memory, but it's not system memory. This mode uses 16 byte (normal) or 64 byte (certain devices, non-standard) of FIFO available for each of the receiver and transmitter, with interrupts based on the FIFO levels. This mode would be used (at the relative low speed of the device) to minimise the time in the interrupt handler. Serial interrupt handlers are still rather instruction intensive (because the 16550 uses a priority encoder, the device can have multiple interrupts pending and all must be serviced before it will generate a new hardware level interrupt). So the obvious answer is the actual answer: to minimise the time software has to take to fill the receive / transmit data buffers Cheers PeteS
Sikandar wrote:
> HI, > > I am using 16550 compatible UART. While this UART supports max speed of > about 11.5 Kbps which is connected to a V92 dialup modem supporting > speeds upto 64Kbps . > > I want to know the logic behind using DMA inside the UART for > transmission to the FIFOs > Is this really required for such low speeds . > > > Regards in anticipation of replies, > Sikandar
Something in your post makes no sense: A 16550 UART supports well above 11.5 kb/s. Do you mean 115kb/s? This depends on manufacturer and the clock used - I have devices rated at 1Mb/s (both commercially and embedded in FPGAs) Cheers PeteS
PeteS wrote:
> Grant Edwards wrote: > > On 2006-07-17, Sikandar <sikandar032@gmail.com> wrote: > > > > > I am using 16550 compatible UART. While this UART supports max > > > speed of about 11.5 Kbps which is connected to a V92 dialup > > > modem supporting speeds upto 64Kbps. > > > > > > I want to know the logic behind using DMA inside the UART for > > > transmission to the FIFOs Is this really required for such low > > > speeds. > > > > There is no DMA inside 16550 UARTs. > > > > -- > > Grant Edwards grante Yow! I'm into SOFTWARE! > > at > > visi.com > > There is a _highly_ misnamed DMA mode 1 and 2 in 16550 compliant UARTS, > which really refers to their FIFO buffering mode. > > This is DMA in the sense the core has direct access to some memory, but > it's not system memory. > > This mode uses 16 byte (normal) or 64 byte (certain devices, > non-standard) of FIFO available for each of the receiver and > transmitter, with interrupts based on the FIFO levels. > > This mode would be used (at the relative low speed of the device) to > minimise the time in the interrupt handler. Serial interrupt handlers > are still rather instruction intensive (because the 16550 uses a > priority encoder, the device can have multiple interrupts pending and > all must be serviced before it will generate a new hardware level > interrupt). > > So the obvious answer is the actual answer: to minimise the time > software has to take to fill the receive / transmit data buffers > > Cheers > > PeteS
What does Serial interrupt handlers are still rather instruction intensive mean ? So the work of DMA is to transfer data from some memory to the FIFOs and generate an interrupt (say after 1/4 or 3/4 of the 16k/ 64k FIFO buffer depending on the size is free/filled ) .In case if we dont use DMA it means that an interrupt is generated for every byte of data received or transmitted . Please correct me if wrong . Regards, Sikandar
Sikandar wrote:
> PeteS wrote: > > Grant Edwards wrote: > > > On 2006-07-17, Sikandar <sikandar032@gmail.com> wrote: > > > > > > > I am using 16550 compatible UART. While this UART supports max > > > > speed of about 11.5 Kbps which is connected to a V92 dialup > > > > modem supporting speeds upto 64Kbps. > > > > > > > > I want to know the logic behind using DMA inside the UART for > > > > transmission to the FIFOs Is this really required for such low > > > > speeds. > > > > > > There is no DMA inside 16550 UARTs. > > > > > > -- > > > Grant Edwards grante Yow! I'm into SOFTWARE! > > > at > > > visi.com > > > > There is a _highly_ misnamed DMA mode 1 and 2 in 16550 compliant UARTS, > > which really refers to their FIFO buffering mode. > > > > This is DMA in the sense the core has direct access to some memory, but > > it's not system memory. > > > > This mode uses 16 byte (normal) or 64 byte (certain devices, > > non-standard) of FIFO available for each of the receiver and > > transmitter, with interrupts based on the FIFO levels. > > > > This mode would be used (at the relative low speed of the device) to > > minimise the time in the interrupt handler. Serial interrupt handlers > > are still rather instruction intensive (because the 16550 uses a > > priority encoder, the device can have multiple interrupts pending and > > all must be serviced before it will generate a new hardware level > > interrupt). > > > > So the obvious answer is the actual answer: to minimise the time > > software has to take to fill the receive / transmit data buffers > > > > Cheers > > > > PeteS > > > > What does Serial interrupt handlers are still rather instruction > intensive mean ? > > So the work of DMA is to transfer data from some memory to the FIFOs > and > generate an interrupt (say after 1/4 or 3/4 of the 16k/ 64k FIFO buffer > depending on the size is free/filled ) .In case if we dont use DMA it > means that an interrupt is generated for every byte of data received > or transmitted . > Please correct me if wrong . > > Regards, > > Sikandar
Instruction intensive means the device may require a lot of instructions to handle an interrupt. As to the operation of the device, you are roughly correct. I suggest reading the datasheet as it is all quite clear in there. Typical datasheet available here: http://www.semiconductors.philips.com/pip/SC16C550-05.html I will note that if you intend to write code for hardware directly, you have to have some understanding of the hardware. Get the datasheet first, and then ask about the parts you don't understand. Cheers PeteS