H8s/2144 interrupts

I have two interrupt sources. ( serial comms & a timer overflow). What I
would like to do is have the timer interrupt set at a higher priority so
that it can interrupt the serial interrupt ISR.

I have set the ICR timer bit hi and the SYSCR INTM0 bit hi but the comms is
still holding off the timer.

I see a reference to I & UI bits. What are they?

Does anyone know how to do this.

TIA

Arthur Richards

Arthur Richards wrote:
> I have two interrupt sources. ( serial comms & a timer overflow). What I
> would like to do is have the timer interrupt set at a higher priority so
> that it can interrupt the serial interrupt ISR.
> 
> I have set the ICR timer bit hi and the SYSCR INTM0 bit hi but the comms is
> still holding off the timer.

What do you mean by "holding"? In most cases one can live with single 
priority level, as interrupt routine should be very short and not cause 
noticeable delays in servicing another interrupt.
Before going for 2 levels, check your serial int routine.

> I see a reference to I & UI bits. What are they?

Roughly what you are looking for.

> Does anyone know how to do this.

I did my very complicated, real time project using 2 serial ports, DMA 
and >4 timer interrupts without going for 2 priority levels.
I don't say it's always feasible, but it is always worth trying.

Hi,

as far as I remember is the priority only concerning pending interrupts.

While an interrupt routine is being executed, no other interrupt can take 
over, regardless priority.

And this is the reason why the interrupt routines must be kept (extremely) 
short.

It could be very anarchical with nested interrupts, the 2134 (which I know 
best) has about 40 interrupt sources.

Are you running serial communication at high speed or do you perform heavy 
dispatching in the reciever interrupts?


Regards

Jens


"Arthur Richards" <fake@address.com.au> skrev i en meddelelse 
news:clnmf4$4k5$1@news-02.connect.com.au...
>I have two interrupt sources. ( serial comms & a timer overflow). What I
> would like to do is have the timer interrupt set at a higher priority so
> that it can interrupt the serial interrupt ISR.
>
> I have set the ICR timer bit hi and the SYSCR INTM0 bit hi but the comms 
> is
> still holding off the timer.
>
> I see a reference to I & UI bits. What are they?
>
> Does anyone know how to do this.
>
> TIA
>
> Arthur Richards
>
>
> 

Thanks for your reply. I have done a bit more reading since I first posted.

I think you are right about the priority affecting pending interrupts only.
It seems that the trick in my case is to set the timer interrupt priority hi
then clear the CPU UI bit during the coms interrupt. This will enable the
timer interrupt (I think).

In the meantime I have also rearranged my comms code a bit to reduce the
latency of the timer interrupt.
Thanks to Grzegorz Mazur for pointing that out.

Thanks,

Arthur




"Jens Gydesen" <jegy@REMOVETHISget2net.dk> wrote in message
news:417ff815$0$207$edfadb0f@dread11.news.tele.dk...
> Hi,
>
> as far as I remember is the priority only concerning pending interrupts.
>
> While an interrupt routine is being executed, no other interrupt can take
> over, regardless priority.
>
> And this is the reason why the interrupt routines must be kept (extremely)
> short.
>
> It could be very anarchical with nested interrupts, the 2134 (which I know
> best) has about 40 interrupt sources.
>
> Are you running serial communication at high speed or do you perform heavy
> dispatching in the reciever interrupts?
>
>
> Regards
>
> Jens
>
>
> "Arthur Richards" <fake@address.com.au> skrev i en meddelelse
> news:clnmf4$4k5$1@news-02.connect.com.au...
> >I have two interrupt sources. ( serial comms & a timer overflow). What I
> > would like to do is have the timer interrupt set at a higher priority so
> > that it can interrupt the serial interrupt ISR.
> >
> > I have set the ICR timer bit hi and the SYSCR INTM0 bit hi but the comms
> > is
> > still holding off the timer.
> >
> > I see a reference to I & UI bits. What are they?
> >
> > Does anyone know how to do this.
> >
> > TIA
> >
> > Arthur Richards
> >
> >
> >
>
>