mw wrote:> R Adsett wrote: > >> I've had this assertion made to me several times. So far no-one has >> been able to back it up. A CPLD capable of holding 4 10 bit PWMs >> always seems to be rather more expensive than a few dollars (You still >> have to add A/D micro etc and fit in the $6 range remember). >> From what I've seen so far it's always cheaper to add another micro to >> act as a PWM peripheral that to add a CPLD to do the same thing. >> >> That's not to say it's impossible, but so far no-ones been able to >> demonstrate that it's doable. >> >> Robert > > > Agreed. Why doesn't someone sell a dedicated chip as a PWM expander? It > would be nice to find a SPI or I2C - compatible chip with 6 to 8 PWM > outputs, at least 14 bits, for LED lighting applications. Preferably in > a 14 or 16 -pin package, 5V compatible outputs. > > All the micros are skimpy on hi-resolution PWM outputs.They do : try these http://www.standardproducts.philips.com/products/bitdisplays/ 4-16 PWM drives, and also blink... -jg
Micro with 4-independent PWM channels
Started by ●January 22, 2005
Reply by ●January 29, 20052005-01-29
Reply by ●January 29, 20052005-01-29
In article <41fbe295@clear.net.nz>, no.spam@designtools.co.nz says...> mw wrote: > > Agreed. Why doesn't someone sell a dedicated chip as a PWM expander? It > > would be nice to find a SPI or I2C - compatible chip with 6 to 8 PWM > > outputs, at least 14 bits, for LED lighting applications. Preferably in > > a 14 or 16 -pin package, 5V compatible outputs. > > > > All the micros are skimpy on hi-resolution PWM outputs. > > They do : try these > http://www.standardproducts.philips.com/products/bitdisplays/ > > 4-16 PWM drives, and also blink...It's not high resolution (only 8 bits), rather slow, and it's really only two PWMs mapped to 4-16 outputs. I can see where it would be useful for LED displays and even as a pre-driver for controlling coil driven devices (such as contactors). I've added it to my interesting devices list. Robert
Reply by ●January 29, 20052005-01-29
> >Agreed. Why doesn't someone sell a dedicated chip as a PWM expander? > >It would be nice to find a SPI or I2C - compatible chip with 6 to 8 PWM > >outputs, at least 14 bits, for LED lighting applications. Preferably in > > a 14 or 16 -pin package, 5V compatible outputs. > > > >All the micros are skimpy on hi-resolution PWM outputs. > > For LED driving it's so so easy to program allmost any micro to performthis> function. You dont need dedicated PWM chanells, you can do it in softwareas> long as the frequency is not too high.I did 48 x 10 bit PWM timers in the FPSLIC once, using about half of 5000 gates, but then I did not need more... -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic AB
Reply by ●January 30, 20052005-01-30
On Sat, 29 Jan 2005 23:19:00 +0100, "Ulf Samuelsson" <ulf@a-t-m-e-l.com> wrote:>> >Agreed. Why doesn't someone sell a dedicated chip as a PWM expander? >> >It would be nice to find a SPI or I2C - compatible chip with 6 to 8 PWM >> >outputs, at least 14 bits, for LED lighting applications. Preferably in >> > a 14 or 16 -pin package, 5V compatible outputs. >> > >> >All the micros are skimpy on hi-resolution PWM outputs. >> >> For LED driving it's so so easy to program allmost any micro to perform >this >> function. You dont need dedicated PWM chanells, you can do it in software >as >> long as the frequency is not too high. > >I did 48 x 10 bit PWM timers in the FPSLIC once, >using about half of 5000 gates, but then I did not need more...So I presume, this is now in an appnote ? Can you provide an URL ? Regards Anton Erasmus
Reply by ●January 30, 20052005-01-30
> >I did 48 x 10 bit PWM timers in the FPSLIC once, > >using about half of 5000 gates, but then I did not need more... > > So I presume, this is now in an appnote ? Can you provide an URL ? > > Regards > Anton ErasmusIt was done, but the Appnote never got finished. So much to do... -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic AB
Reply by ●January 30, 20052005-01-30
In article <362l9fF4sr2l7U1@individual.net>, ulf@a-t-m-e-l.com says...> > I did 48 x 10 bit PWM timers in the FPSLIC once, > using about half of 5000 gates, but then I did not need more...Sounds intriguing. What frequency could you run them at? Robert
Reply by ●January 30, 20052005-01-30
"R Adsett" <radsett@junk.aeolusdevelopment.cm> skrev i meddelandet news:6qmdnZvXR-wUmGDcRVn-vg@rogers.com...> In article <362l9fF4sr2l7U1@individual.net>, ulf@a-t-m-e-l.com says... > > > > I did 48 x 10 bit PWM timers in the FPSLIC once, > > using about half of 5000 gates, but then I did not need more... > > Sounds intriguing. What frequency could you run them at? > > RobertThe FPGA portion ran at 25 MHz. Design was really simple. A 64 bit x 16 SRAM was implemented in the internal DPRAMs. 10 bits of each word, allocated to an event time. 6 bits allocated to a "timer number". 64 words means that I support 64 timers. The timers have to be "sorted" according to PWM length.. The shortest PWM length is in position #0 in the SRAM. The main blocks of the timer is * A state machine controlling which value should be written to a timer output.. * A 10 bit counter/comparator connected to the SRAM "event" * An address register for the SRAM. In state 1, the address counter counts from 0..47. The event counter is also started. The state machine ensures that outputs selected though the "timer number" in the SRAM are set. In state 2, the address is reset to zero, addressing word 0. Any timer output selected here, will be cleared. The event counter continues to count and will have reached 48 at this point. When (SRAM.event[adr] == counter), the timer output is cleared and the address register is incremented to point at the next counter. There are a few limitations with this. It is not rail to rail. A PWM output can only be high from 0..(1024-48) so you lose 5% of the duty cycle. Two timers cannot change value at the same time. The end customer thought this was nice, since toggling 48 outputs simultaneously caused ground bounce. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.
Reply by ●January 31, 20052005-01-31
In article <3658gdF4vm8piU1@individual.net>, ulf@NOSPAMatmel.com says...> "R Adsett" <radsett@junk.aeolusdevelopment.cm> skrev i meddelandet > news:6qmdnZvXR-wUmGDcRVn-vg@rogers.com... > > In article <362l9fF4sr2l7U1@individual.net>, ulf@a-t-m-e-l.com says... > > > > > > I did 48 x 10 bit PWM timers in the FPSLIC once, > > > using about half of 5000 gates, but then I did not need more... > > > > Sounds intriguing. What frequency could you run them at? > > The FPGA portion ran at 25 MHz.So that would be a 25kHz (or so) PWM?> A 64 bit x 16 SRAM was implemented in the internal DPRAMs. > > 10 bits of each word, allocated to an event time. > 6 bits allocated to a "timer number". > 64 words means that I support 64 timers. > > The timers have to be "sorted" according to PWM length.. > The shortest PWM length is in position #0 in the SRAM. > > The main blocks of the timer is > * A state machine controlling which value should be written to a timer > output.. > * A 10 bit counter/comparator connected to the SRAM "event" > * An address register for the SRAM. > > In state 1, the address counter counts from 0..47. > The event counter is also started. > The state machine ensures that outputs selected though the "timer number" > in the SRAM are set. > > In state 2, the address is reset to zero, addressing word 0. > Any timer output selected here, will be cleared. > The event counter continues to count and will have reached 48 at this point. > When (SRAM.event[adr] == counter), the timer output is cleared > and the address register is incremented to point at the next counter.I can see a few other (non-pwm) potential uses for this type of structure. If you ever do write up an appnote it sounds like it would be an interesting read. Robert
