On Sun, 26 Nov 2006 22:35:19 +0100, Rene Tschaggelar <none@none.net> wrote:>Jim Thompson wrote: >> On Sun, 26 Nov 2006 20:14:36 GMT, Vladimir Vassilevsky >> <antispam_bogus@hotmail.com> wrote: >> >[snip] > >> Allowing a static (and *undefined* BTW... 1mA if you're lucky) current >> flow is NOT good engineering practice, and it's NEVER done in >> well-designed ASIC's. >> >> To see how a 3.3V Logic Level to 5V Logic Level Translator is done >> properly (in ASIC's designed specifically for that purpose), see... >> >> http://analog-innovations.com/SED/LogicLevelTranslator.pdf > >Jim, >your schematic is lacking the power details. >How are the HC04 powered ? +3.3V or +5V ? > >ReneFrom InverterVDD... Those PSpice-provided inverter symbols utilize "hidden" power pins. In the USB ASIC there weren't actually full 74HC04 equivalents, just single-stage min-geometry inverters... going on into the ASIC... i.e. no heavy loading. ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
3.3v <> 5v interfacing @ 15Mhz
Started by ●November 25, 2006
Reply by ●November 26, 20062006-11-26
Reply by ●November 26, 20062006-11-26
Jim Thompson wrote:>>>> If you have something meaningful to say, then go ahead and tell us. >>>> Otherwise have the courage to admit that you just made a fool of >>>> yourself, my dear analog desiner. >>>> >>> Apply +2.4V Input to an HCTxx running on VDD = +5V and what happens? >>> >> >> Nothing happens. The 2.4V reads as a clear 1, the threshold is at 1.4V >> +/- hysteresis of 100mV, the propagation delay is about 5ns/10ns >> fall/raise accordingly. The current consumption at 2.4Vin/5Vdd is 1mA >> which is perfectly within the allowed limits. >> >> Jim , you goofed up and I suggest you to bring your apologies. > > Allowing a static (and *undefined* BTW... 1mA if you're lucky)RTFM. http://focus.ti.com/docs/prod/folders/print/sn74hct04.html http://www.ti.com/lit/gpn/sn74hct04 ... page 3. electrical characteristics over recommended operating free-air temperature range ΔICC(*), One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC, 2.9mA *max*. (*) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.> I used a similar scheme in my USB interface work for Intel.Irrelevant. There was a very specific problem, and HCT/AHCT is a correct solution.> Expect my apologies about the time Russia actually becomes a Democracy > and Iran becomes Jewish ;-)Very few people can accept their own mistakes, unfortunately. Life would be much better otherwise. -- WBR, Yuriy. "Resistance is futile"
Reply by ●November 26, 20062006-11-26
"Yuriy K." <yktech@mail.ru> wrote: > Jim Thompson wrote: [...] >> Allowing a static (and *undefined* BTW. 1mA if you're lucky) > RTFM. > http://www.ti.com/lit/gpn/sn74hct04 > page 3. > electrical characteristics over recommended operating free-air > temperature range > �ICC(*), One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC, > 2.9mA *max*. > (*) This is the increase in supply current for each input that is > at one of the specified TTL voltage levels, rather than 0 V or > VCC. >> I used a similar scheme in my USB interface work for Intel. > Irrelevant. There was a very specific problem, and HCT/AHCT is a > correct solution. Yuriy, You are correct. Here's more supporting documentation. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ AHC/AHCT Designer's Guide September 1998, revised February 2000 Starting on page 19: To process signals having a swing of only about 3 V in a system with a supply voltage of 5 V, the TTL-compatible SN74AHCT14 Schmitt trigger is available. This device has the same switching characteristics as the previously described Schmitt trigger, except that appropriate circuitry shifts the switching thresholds into the region of the commonly used TTL-voltage levels. Figure 5 shows the transfer function of such components. http://focus.ti.com/lit/ml/scla013d/scla013d.pdf ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ SN54/74HCT CMOS Logic Family Applications and Restrictions Power Consumption of HCT Circuits The threshold voltage of a CMOS circuit is determined by the geometry of the input transistors. These transistors are designed to sink the same input current at the required threshold voltage. The resulting voltage at the output is equivalent to 50% of the supply voltage VCC. For an HC circuit, the channel width of the p-channel transistor of the input is approximately twice the value of an n-channel transistor. The purpose is to make both transistors have the same current characteristics, thus making the threshold voltage of their input at about 50% of the supply voltage VCC. This circuit area has been modified for HCT devices: the n-channel transistor is about seven times wider than the p-channel transistor (see Figure 6). This shifts the threshold voltage in a way that it amounts to 30% of the supply voltage. At a supply voltage VCC = 5 V, the threshold voltage is VT = 1.5 V, similar to the threshold voltage of TTL circuits. Figure 6. Input-Stage Structure of HC and HCT Circuits Figure 7. Supply Current as a Function of the Input Voltage Figure 8. Current Consumption as a Function of Frequency For frequencies above 5 MHz, this effect is of secondary importance, since current consumption is then determined primarily by the power required for reversing the charge of the load capacitance. Moreover, the increase of current consumption for devices driven by TTL levels is much lower in practice because TTL circuits supply a typical voltage swing that is significantly higher than the data sheet value used for the measurement in Figure 8. http://focus.ti.com/lit/an/scla011/scla011.pdf ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Regards, Mike Monett Antiviral, Antibacterial Silver Solution: http://silversol.freewebpage.org/index.htm SPICE Analysis of Crystal Oscillators: http://silversol.freewebpage.org/spice/xtal/clapp.htm Noise-Rejecting Wideband Sampler: http://www3.sympatico.ca/add.automation/sampler/intro.htm
Reply by ●November 26, 20062006-11-26
Alison, http://www-s.ti.com/sc/psheets/scea035a/scea035a.pdf is a explanation of the different logic level voltage translation methods and ICs. -- WBR, Yuriy. "Resistance is futile"
Reply by ●November 26, 20062006-11-26
Jim Thompson wrote:> On Sun, 26 Nov 2006 20:14:36 GMT, Vladimir Vassilevsky > <antispam_bogus@hotmail.com> wrote: > >> >> >>Jim Thompson wrote: >> >>>>>>>>Incredible. Designing complicated circuit instead of simply using >>>>>>>>74HCT14 / 74HCT04 / zillion other HCT74xx and AHCTxx ICs. >>>>>>>You've just proved yourself an incredible dumb-shit ;-) >>>>> >>>>>Keep it up. Everybody is realizing the "value" of your consultancy >>>>>;-) >>>>> >>>>>You read a data sheet without understanding. >>>>> >>>>> ...Jim Thompson >>>> >>>> >>>> >>>>If you have something meaningful to say, then go ahead and tell us. >>>>Otherwise have the courage to admit that you just made a fool of >>>>yourself, my dear analog desiner. >>>> >>>> >>> >>> Apply +2.4V Input to an HCTxx running on VDD = +5V and what happens? >>> >> >> >>Nothing happens. The 2.4V reads as a clear 1, the threshold is at 1.4V >>+/- hysteresis of 100mV, the propagation delay is about 5ns/10ns >>fall/raise accordingly. The current consumption at 2.4Vin/5Vdd is 1mA >>which is perfectly within the allowed limits. >> >>Jim , you goofed up and I suggest you to bring your apologies. >> >>Vladimir Vassilevsky >> >>DSP and Mixed Signal Design Consultant >> >>http://www.abvolt.com >> >> > > Allowing a static (and *undefined* BTW... 1mA if you're lucky) current > flow is NOT good engineering practice, and it's NEVER done in > well-designed ASIC's. > > To see how a 3.3V Logic Level to 5V Logic Level Translator is done > properly (in ASIC's designed specifically for that purpose), see... > > http://analog-innovations.com/SED/LogicLevelTranslator.pdf > > Dimensions are "pre-shrink" BTW, as if you'd know what that means ;-) > > I used a similar scheme in my USB interface work for Intel. > Unfortunately the patents don't show that part, since it's old art. > > Expect my apologies about the time Russia actually becomes a Democracy > and Iran becomes Jewish ;-) > > ...Jim ThompsonI think that in the non-ASIC world where adding extra transistors is not free, it is less frowned-upon to allow CMOS logic to draw continuous supply current. I don't know of any chips failing due to doing this, with the exception of 74AC series when running from 5V and biased at the threshold, which really does draw a lot of current. OnSemi do in fact recommend the use of HCT14 devices to receive signals from LSTTL chips (see for yourself.... perhaps their marketing dept needs re-education): http://www.onsemi.com/PowerSolutions/product.do?id=MC74HCT14ADT The datasheet "Recommended Operating Conditions" explicitly specifies that there is no minimum input slew rate, and the supply current with one input held at 2.4V is specified as 2.4mA (typ), implying that it is at least an allowable operating condition. Certainly 2.4mA is far below the specified maximum IDD for the part. It seems to me that the HCT14 will work, and not fail prematurely, when one inverter is driven by a 3.3V input signal. Perhaps you know better, and if so I'd like to hear about it. I think your circuit with no steady state current consumption would be ideal if one were designing an ASIC, but the intended application is not battery powered, and the HCT parts are cheap, available from several sources, less likely to be discontinued than an exotic level shifter IC, and result in lower component count than using an additional CD4007 (which would probably be too slow anyway when it's required to go to 15MHz). BTW why is the simulated waveform from your CD4007 circuit so fast? Perhaps you don't have PCB parasitics in your simulation. Most manufacturers of 4007 parts seem to specify about 60 - 75ns maximum propagation delay at 5V VDD. I wonder if anyone makes a CD4007 type thing in a more modern process. Chris
Reply by ●November 26, 20062006-11-26
On Sun, 26 Nov 2006 18:00:38 -0500, Mike Monett <No@email.adr> wrote: [snip]> > Figure 7. Supply Current as a Function of the Input Voltage >[snip]> > http://focus.ti.com/lit/an/scla011/scla011.pdf > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Regards, > > Mike Monett >If you're comfortable with that "overlap" current, go right ahead. I still consider it bad engineering practice but, then again, I'm presently designing a chip (analog, but LOTS of logic) with a total average power consumption specification of 6uA. Overlaps like that would kill the consumption. I do note that the TI app-note does recommend the Schmitt. But it depends on the Schmitt design whether you still have the overlap current or not. If 'HCT04 were a good general solution to 3.3V to 5V translators, wonder why they make true translator chips like the Maxim MX3xxxx to name just one? For their health? I doubt it. ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●November 26, 20062006-11-26
Jim Thompson wrote:>>Jim Thompson wrote: >> >> >>>>>>>>Incredible. Designing complicated circuit instead of simply using >>>>>>>>74HCT14 / 74HCT04 / zillion other HCT74xx and AHCTxx ICs. >>>>>>>You've just proved yourself an incredible dumb-shit ;-) >>>>>Keep it up. Everybody is realizing the "value" of your consultancy >>>>>;-) >>>>> >>>>>You read a data sheet without understanding. >>>>> >>>>> ...Jim Thompson >>>> >>>> >>>>>>>>If you have something meaningful to say, then go ahead and tell us. >>>>Otherwise have the courage to admit that you just made a fool of >>>>yourself, my dear analog desiner.>>> >>>Apply +2.4V Input to an HCTxx running on VDD = +5V and what happens? >>> >> >> >>Nothing happens. The 2.4V reads as a clear 1, the threshold is at 1.4V >>+/- hysteresis of 100mV, the propagation delay is about 5ns/10ns >>fall/raise accordingly. The current consumption at 2.4Vin/5Vdd is 1mA >>which is perfectly within the allowed limits. >>> Allowing a static (and *undefined* BTW... 1mA if you're lucky) current > flow is NOT good engineering practice, and it's NEVER done in > well-designed ASIC's.Will you cut down the bullshit about ASICs, USB and nanoamperes. We are talking about interfacing the 3.3V CMOS input level from a flash card to 5V level input of a dsPIC. It is perfectly done with a simple 74HCT gate, and this solution you can find in any ABC book on electronics. BTW, where did you get the 2.4V? JFYI: for 3.3V CMOS level and 5Vdd, the consumption is just 0.3mA. This is a perfectly documented mode of the operation, RTFM.> > To see how a 3.3V Logic Level to 5V Logic Level Translator is done > properly (in ASIC's designed specifically for that purpose), see... > > http://analog-innovations.com/SED/LogicLevelTranslator.pdf > > Dimensions are "pre-shrink" BTW, as if you'd know what that means ;-)I don't care. It is absolutely irrelevant.> I used a similar scheme in my USB interface work for Intel. > Unfortunately the patents don't show that part, since it's old art.You see, grandpa, what you are doing is too old fashioned.> Expect my apologies about the time Russia actually becomes a DemocracyThere is no such thing as Russia. There was, there is and there will always be the USSR. Unfortunately.> and Iran becomes Jewish ;-)Very well could be. The jews of Israel are actually changing to arab-like nation. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●November 26, 20062006-11-26
rickman <gnuarm@gmail.com> wrote in message news:1164556090.180281.211180@n67g2000cwd.googlegroups.com...> Yes, it does look a little rough. I don't think many people still use > those push boards just because they can create problem with the speeds > of today's circuits. The stuff we do goes directly to PCB. In fact > the last board I designed had *no* artwork revisions and the first rev > is being shipped to the customer now. > >Hi Rickman, It's looking alot tidier now. Should keep me going with the firmware development until the PCBs appear. http://www.logicsays.com/pub/WeST/WeST_v2.jpg The board with the chip on it has most of what's required SPI side condensed down. There's a board under that takes care of getting the Vdd/Vss to the all of the pins (PICs are picky about that). And the ribbon cable goes off to a kind of hybrid SCSI bus implemented on a 68000 processor DMA bus. Thanks again for your help :-) Thanks to all of you :-) Alison
Reply by ●November 26, 20062006-11-26
Alison wrote:> rickman <gnuarm@gmail.com> wrote in message > news:1164556090.180281.211180@n67g2000cwd.googlegroups.com... > > Yes, it does look a little rough. I don't think many people still use > > those push boards just because they can create problem with the speeds > > of today's circuits. The stuff we do goes directly to PCB. In fact > > the last board I designed had *no* artwork revisions and the first rev > > is being shipped to the customer now. > > > > > > Hi Rickman, > > It's looking alot tidier now. Should keep me going with the firmware > development until the PCBs appear. > > http://www.logicsays.com/pub/WeST/WeST_v2.jpg > > The board with the chip on it has most of what's required SPI side condensed > down. There's a board under that takes care of getting the Vdd/Vss to the > all of the pins (PICs are picky about that). And the ribbon cable goes off > to a kind of hybrid SCSI bus implemented on a 68000 processor DMA bus. > > Thanks again for your help :-) Thanks to all of you :-) > > AlisonIf you run into problems, then as I live near Cambridge (work near there too), I might be willing to help you out - think of it as a xmas gift or whatever. Cheers PeteS
Reply by ●November 26, 20062006-11-26
On Mon, 27 Nov 2006 00:12:23 GMT, Vladimir Vassilevsky <antispam_bogus@hotmail.com> wrote:> > >Jim Thompson wrote: > >>>Jim Thompson wrote: >>> >>> >>>>>>>>>Incredible. Designing complicated circuit instead of simply using >>>>>>>>>74HCT14 / 74HCT04 / zillion other HCT74xx and AHCTxx ICs. >>>>>>>>You've just proved yourself an incredible dumb-shit ;-) >>>>>>Keep it up. Everybody is realizing the "value" of your consultancy >>>>>>;-) >>>>>> >>>>>>You read a data sheet without understanding. >>>>>> >>>>>> ...Jim Thompson >>>>> >>>>> >>>>> > >>>>>If you have something meaningful to say, then go ahead and tell us. >>>>>Otherwise have the courage to admit that you just made a fool of >>>>>yourself, my dear analog desiner. > >>>> >>>>Apply +2.4V Input to an HCTxx running on VDD = +5V and what happens? >>>> >>> >>> >>>Nothing happens. The 2.4V reads as a clear 1, the threshold is at 1.4V >>>+/- hysteresis of 100mV, the propagation delay is about 5ns/10ns >>>fall/raise accordingly. The current consumption at 2.4Vin/5Vdd is 1mA >>>which is perfectly within the allowed limits. >>> > >> Allowing a static (and *undefined* BTW... 1mA if you're lucky) current >> flow is NOT good engineering practice, and it's NEVER done in >> well-designed ASIC's. > >Will you cut down the bullshit about ASICs, USB and nanoamperes. We are >talking about interfacing the 3.3V CMOS input level from a flash card to >5V level input of a dsPIC. It is perfectly done with a simple 74HCT >gate, and this solution you can find in any ABC book on electronics. > >BTW, where did you get the 2.4V? JFYI: for 3.3V CMOS level and 5Vdd, the >consumption is just 0.3mA. This is a perfectly documented mode of the >operation, RTFM. > > >> >> To see how a 3.3V Logic Level to 5V Logic Level Translator is done >> properly (in ASIC's designed specifically for that purpose), see... >> >> http://analog-innovations.com/SED/LogicLevelTranslator.pdf >> >> Dimensions are "pre-shrink" BTW, as if you'd know what that means ;-) > >I don't care. It is absolutely irrelevant. > >> I used a similar scheme in my USB interface work for Intel. >> Unfortunately the patents don't show that part, since it's old art. > >You see, grandpa, what you are doing is too old fashioned. > > >> Expect my apologies about the time Russia actually becomes a Democracy > >There is no such thing as Russia. There was, there is and there will >always be the USSR. Unfortunately. > >> and Iran becomes Jewish ;-) > >Very well could be. The jews of Israel are actually changing to >arab-like nation. > >Vladimir Vassilevsky > >DSP and Mixed Signal Design Consultant > >http://www.abvolt.comThere is no way to argue with a punk. Don't go away mad, just go away. When your accumulated income exceeds $5 million, *perhaps* I'll deign to listen to you ;-) ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
