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Reset should not clear SRAM

Started by karthikbg January 9, 2007
Hi,

My SRAM ranges from 20000000 to 2003E7FF (250Kbytes) in OMAP 5912 .I
have some data stored in it by my application, so that it can be used
by my application when it gets loaded after reset .
But, When i  reset my OMAP 5912 processor by configuring the ARM_RSTCT1
to 0x08,(Global reset ) i find that SRAM gets cleared.

But, 0x08 actually implies Reseting of DSP, MPU and Peripherals only
.(No relation with SRAM contents ) .So, how could by SRAM get cleared ?


I find that in the Boot ROM code , MPU peripherals are enabled by
configuring ARM_RSTCT2 to 0x0001.

In the bootloader code i have,
ARM_RSTCT2  = 0x0001; //MPU peripherals are enabled here.
ARM_RSTCT1  = 0x004;  //Priority registers and EMIF can be programmed
ARM_RSTCT1  = 0x006;  //ReleaseDSPFromReset here.

I do not find anything that could cause the SRAM contents to be cleared
either in Boot ROM, Bootloader or Application.

But, how does my SRAM contents get cleared ?

Kindly share your views/ideas regarding this .

Thx in advans,
Karthik Balaguru

karthikbg wrote:
> Hi, > > My SRAM ranges from 20000000 to 2003E7FF (250Kbytes) in OMAP 5912 .I > have some data stored in it by my application, so that it can be used > by my application when it gets loaded after reset . > But, When i reset my OMAP 5912 processor by configuring the ARM_RSTCT1 > to 0x08,(Global reset ) i find that SRAM gets cleared. > > But, 0x08 actually implies Reseting of DSP, MPU and Peripherals only > .(No relation with SRAM contents ) .So, how could by SRAM get cleared ? > > > I find that in the Boot ROM code , MPU peripherals are enabled by > configuring ARM_RSTCT2 to 0x0001. > > In the bootloader code i have, > ARM_RSTCT2 = 0x0001; //MPU peripherals are enabled here. > ARM_RSTCT1 = 0x004; //Priority registers and EMIF can be programmed > ARM_RSTCT1 = 0x006; //ReleaseDSPFromReset here. > > I do not find anything that could cause the SRAM contents to be cleared > either in Boot ROM, Bootloader or Application. > > But, how does my SRAM contents get cleared ? > > Kindly share your views/ideas regarding this . > > Thx in advans, > Karthik Balaguru >
Perhaps your gel file clears the SRAM in the OnReset callback function.
Brad Griffis wrote:
> karthikbg wrote: > > Hi, > > > > My SRAM ranges from 20000000 to 2003E7FF (250Kbytes) in OMAP 5912 .I > > have some data stored in it by my application, so that it can be used > > by my application when it gets loaded after reset . > > But, When i reset my OMAP 5912 processor by configuring the ARM_RSTCT1 > > to 0x08,(Global reset ) i find that SRAM gets cleared. > > > > But, 0x08 actually implies Reseting of DSP, MPU and Peripherals only > > .(No relation with SRAM contents ) .So, how could by SRAM get cleared ? > > > > > > I find that in the Boot ROM code , MPU peripherals are enabled by > > configuring ARM_RSTCT2 to 0x0001. > > > > In the bootloader code i have, > > ARM_RSTCT2 = 0x0001; //MPU peripherals are enabled here. > > ARM_RSTCT1 = 0x004; //Priority registers and EMIF can be programmed > > ARM_RSTCT1 = 0x006; //ReleaseDSPFromReset here. > > > > I do not find anything that could cause the SRAM contents to be cleared > > either in Boot ROM, Bootloader or Application. > > > > But, how does my SRAM contents get cleared ? > > > > Kindly share your views/ideas regarding this . > > > > Thx in advans, > > Karthik Balaguru > > > > Perhaps your gel file clears the SRAM in the OnReset callback function.
Thx for the info. But, Gel file comes into picture, only if i debug using CCS (Code Composer Studio). But, here my SRAM gets cleared in realtime scenario. (Without any debug environment that uses CCS). Does TI OMAP 5912 have something else that takes control after reset and clears the SRAM ? Share your views/ideas regarding this. Is there anything internally in OMAP 5912 that handles the request before passing the interrupt to the IVT and branching to the corresponding location ? Does TI OMAP 5912 have something else that takes control after reset and clears the SRAM ? Thx in advans, Karthik Balaguru
karthikbg wrote:

> > But, here my SRAM gets cleared in realtime scenario. (Without any debug > environment that uses CCS). >
Would it be the C startup code cleared the "zero initialize" region, which included your SRAM? Joseph
karthikbg wrote:

   ...

> Does TI OMAP 5912 have something else that takes control after reset > and clears the SRAM ?
Is the static RAM external? If so, have you put a scope on the Read/~Write line? Is there a master clear line to the memory? Jerry -- Engineering is the art of making what you want from things you can get. �����������������������������������������������������������������������
Jerry Avins wrote:
> karthikbg wrote: > > ... > > > Does TI OMAP 5912 have something else that takes control after reset > > and clears the SRAM ? > > Is the static RAM external? If so, have you put a scope on the > Read/~Write line? Is there a master clear line to the memory? > > Jerry > -- > Engineering is the art of making what you want from things you can get. > =AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=
=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF= =AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF=AF Hi, It is the SRAM (Framebuffer) area of the processor. It is internal memory only. I suspect the contents of it are getting overwritten by TI's internal primary bootloader. But, even it overwrites the contents to a certain range of addresses of SRAM, the remaining contents in SRAM should not get zeroed. Is my assumption correct ? I do not understand how the contents of the SRAM is getting zeroed. Thx in advans, Karthik Balaguru