____SRAM_gets__cleared use CS2 to power

  SRAM has 2 ChipSel  lines , modern CPU with battery backup

 has a std method of safeing SRAM , using this

2nd ChipSelect pin ...   "CS2"
  --------
 SRAM has 2 sizes , small is CMOS ,   5 microamps stdby
  Big is DRAM , 70Microamps  stdby
  but they call it PSRAM .

______________________________________________________-


Thx for the info.  But, Gel file comes into picture, only if i debug
using CCS (Code Composer Studio).

But, here my SRAM gets cleared in realtime scenario. (Without any debug

environment that uses CCS).


Does TI OMAP 5912 have something else that takes control after reset
and clears the SRAM ?


Share your views/ideas regarding this.


Is there anything internally in OMAP 5912 that handles the request
before passing the interrupt to the IVT and branching to the
corresponding location ?


Does TI OMAP 5912 have something else that takes control after reset
and clears the SRAM ?=20


Thx in advans,=20
Karthik Balaguru=20


Reply =BB