I am using a ADSP blackfin Bf533 processor, i have only sport Rcv and Sport Tx Dma configured for ethernet rcv and tx respectively. I run a loopback code to loop packets from sport Rcv to Sport TX (with an intermediate SDRAM copy). Sport Tx dma often stalls and leads to a dma stuck up condition. things i have observed: ----------------------------- (i) DMA stuck up does not occur if intermediate copy is in L1 instead of sdram (ii) If core is kept busy for the duration when Sport Tx Dma is running by using some delay loop (i.e. core does not access anything else.. just waits in a loop till sport Tx dma is complete), then the dma never stalls (even if the intermediate buffer is in SDRAM) Queries: ---------- (i) Does BF533 have a problem with DMA (from L1) and SdRAm access running parallely. ( I tested this in another test code, but found no problems..) (ii) If not, then what else could be the reason for the sport tx Dma stalling.
Dma stalling!
Started by ●February 6, 2007
Reply by ●February 6, 20072007-02-06
adonis wrote:> I am using a ADSP blackfin Bf533 processor, i have only sport Rcv and > Sport Tx Dma configured for ethernet rcv and tx respectively.BF533 does not have the Ethernet controller. What is the relation between SPORT and Ethernet? I run a> loopback code to loop packets from sport Rcv to Sport TX (with an > intermediate SDRAM copy). Sport Tx dma often stalls and leads to a dma > stuck up condition. > > things i have observed: > ----------------------------- > (i) DMA stuck up does not occur if intermediate copy is in L1 instead > of sdram > (ii) If core is kept busy for the duration when Sport Tx Dma is > running by using some delay loop (i.e. core does not access anything > else.. just waits in a loop till sport Tx dma is complete), then the > dma never stalls (even if the intermediate buffer is in SDRAM) > > Queries: > ---------- > (i) Does BF533 have a problem with DMA (from L1) and SdRAm access > running parallely. ( I tested this in another test code, but found no > problems..) > (ii) If not, then what else could be the reason for the sport tx Dma > stalling.Did you set the core/dma bus priority bit in AMGCTL? Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●February 6, 20072007-02-06
On Feb 6, 10:36 am, Vladimir Vassilevsky <antispam_bo...@hotmail.com> wrote:> adonis wrote: > > I am using a ADSP blackfin Bf533 processor, i have only sport Rcv and > > Sport Tx Dma configured for ethernet rcv and tx respectively. > > BF533 does not have the Ethernet controller. What is the relation > between SPORT and Ethernet? > > I run a > > > > > loopback code to loop packets from sport Rcv to Sport TX (with an > > intermediate SDRAM copy). Sport Tx dma often stalls and leads to a dma > > stuck up condition. > > > things i have observed: > > ----------------------------- > > (i) DMA stuck up does not occur if intermediate copy is in L1 instead > > of sdram > > (ii) If core is kept busy for the duration when Sport Tx Dma is > > running by using some delay loop (i.e. core does not access anything > > else.. just waits in a loop till sport Tx dma is complete), then the > > dma never stalls (even if the intermediate buffer is in SDRAM) > > > Queries: > > ---------- > > (i) Does BF533 have a problem with DMA (from L1) and SdRAm access > > running parallely. ( I tested this in another test code, but found no > > problems..) > > (ii) If not, then what else could be the reason for the sport tx Dma > > stalling. > > Did you set the core/dma bus priority bit in AMGCTL? > > Vladimir Vassilevsky > > DSP and Mixed Signal Design Consultant > > http://www.abvolt.comOh yes Vladimir i agree with you, that Bf533 does not have a ethernet controller. I am using an external Realtek Controller 8305SB.. clock fed by the controller to blackfin... the following are the EBIU config: EBIU_AMBCTL0 = 0x7bb07bb0; EBIU_AMBCTL1 = 0x7bb07bb0; EBIU_AMGCTL = 0x00ff;
Reply by ●February 6, 20072007-02-06
adonis wrote:>>>loopback code to loop packets from sport Rcv to Sport TX (with an >>>intermediate SDRAM copy). Sport Tx dma often stalls and leads to a dma >>>stuck up condition. >> >>Did you set the core/dma bus priority bit in AMGCTL? >> > fed by the controller to blackfin... the following are the EBIU > config: > > EBIU_AMBCTL0 = 0x7bb07bb0; > EBIU_AMBCTL1 = 0x7bb07bb0; > EBIU_AMGCTL = 0x00ff;^^^^^^^^^^^^^^^^^^^^^^^^ Wrong config. No wonder DMA gets stuck. CDPRIO should be set. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●February 7, 20072007-02-07
On Feb 6, 11:57 am, Vladimir Vassilevsky <antispam_bo...@hotmail.com> wrote:> adonis wrote: > >>>loopback code to loop packets from sport Rcv to Sport TX (with an > >>>intermediate SDRAM copy). Sport Tx dma often stalls and leads to a dma > >>>stuck up condition. > > >>Did you set the core/dma bus priority bit in AMGCTL? > > > fed by the controller to blackfin... the following are the EBIU > > config: > > > EBIU_AMBCTL0 = 0x7bb07bb0; > > EBIU_AMBCTL1 = 0x7bb07bb0; > > EBIU_AMGCTL = 0x00ff; > > ^^^^^^^^^^^^^^^^^^^^^^^^ > > Wrong config. No wonder DMA gets stuck. > CDPRIO should be set. > > Vladimir Vassilevsky > > DSP and Mixed Signal Design Consultant > > http://www.abvolt.comHey Vladimr, I will surely add that too tomorrow.. CDPRIO should be set.. so my EBIU_AMGCTL should be 0x01ff... but is there anything else to be taken care.. I will update you on the results.. Thank you very much.. Regards, Adonis
Reply by ●February 8, 20072007-02-08
On Feb 7, 8:00 am, "adonis" <vijayvikran...@gmail.com> wrote:> On Feb 6, 11:57 am, Vladimir Vassilevsky <antispam_bo...@hotmail.com> > wrote: > > > > > adonis wrote: > > >>>loopback code to loop packets from sport Rcv to Sport TX (with an > > >>>intermediate SDRAM copy). Sport Tx dma often stalls and leads to a dma > > >>>stuck up condition. > > > >>Did you set the core/dma bus priority bit in AMGCTL? > > > > fed by the controller to blackfin... the following are the EBIU > > > config: > > > > EBIU_AMBCTL0 = 0x7bb07bb0; > > > EBIU_AMBCTL1 = 0x7bb07bb0; > > > EBIU_AMGCTL = 0x00ff; > > > ^^^^^^^^^^^^^^^^^^^^^^^^ > > > Wrong config. No wonder DMA gets stuck. > > CDPRIO should be set. > > > Vladimir Vassilevsky > > > DSP and Mixed Signal Design Consultant > > >http://www.abvolt.com > > Hey Vladimr, > I will surely add that too tomorrow.. CDPRIO should > be set.. > so my EBIU_AMGCTL should be 0x01ff... but is there anything else to > be taken care.. > I will update you on the results.. > Thank you very much.. > > Regards, > AdonisHey, tried Setting the CDPRIO bit also to make dma have higher priority over core access... but the problem still persists... One particular observation that i made today is that it might sport getting stuck than Dma stuck up. Justification: --------------- The sport runs in data dependent mode in my case. Normal configuration: when we want to Tx Enable Dma Enable Sport when Tx done comes (after giving FIFO delay) Disable Dma Disable Sport Now when i notice Dma stuck up problem, i carried out 2 experiments (i) disabling and enabling Dma alone.. not touching peripheral (ii) disabling and enabling Sport tx alone.. not touching Dma My observation is that in case (i) stuck up keeps on happening for consecutive packets also.. continously.. so retrigerring dma does not help in case (ii) the dma data and register pointers are not touched.. sport tx is disabled and enabled.. in this case Dma it recovers and stuck up never happens continously.. So, this should be peripheral getting stuck and not Dma.. Hey Vladimr please tell me if my interpretation is right or am i missing out something.. Please give your suggestions... regards, adonis
Reply by ●February 8, 20072007-02-08
adonis wrote:> > Hey, > tried Setting the CDPRIO bit also to make dma have higher priority > over core access... but the problem still persists... > One particular observation that i made today is that it might sport > getting stuck than Dma stuck up. > Justification:[...]> Hey Vladimr please tell me if my interpretation is right or am i > missing out something.. > Please give your suggestions...I can solve your problems with BlackFin. However this is going to be the business. If you are interested, the email address is at the web site. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
