DSCR register in 68332, sync. stop/start of CPU and TPU

Has anyone here had success doing this? 

When debugging interface between code running in the TPU (Time
Processing Unit), and code running on the "68k" CPU, it would be nice
that both stop and start syncroneously.

According to the manual, this register contains 2 bits controlling
freeze of the TPU.  So, as I understand it, if I write e.g. 0x180 to DSCR
the TPU should stop too, if the CPU stops at a breakpoint.

I added this write to my initialization, but the TPU continues to run,
like before the change. Is there some other register, that should be
written too?

I am using a Lauterbach ICD (BDM debugger) to break and single step
the CPU. 

-- 
mdc at manbw dk  -  MAN Diesel A/S, Copenhagen
www.manbw.com    -  Electronics & software dept.
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