"Jim Granville" <no.spam@designtools.maps.co.nz> skrev i meddelandet news:4601b6da$1@clear.net.nz...> aniloyo2@hiwaay.net wrote: > >> On Mar 20, 4:01 pm, "Ulf Samuelsson" <u...@a-t-m-e-l.com> wrote: >> >>>What is the ADC sample rate and resolution?` >>>What is the DAC sample rate and resolution? >> >> >> 3 MHz, 16 bit ADC >> 3 MHz, 14 bit DAC >> >> >>>Then think SSC which can run at Master Clock (96 Mhz) / 2 = 48 MHz. >>>With a 16 bit ADC/DAC, you can get 3 MSamples/s in both directions. >>>With an 8 bit ADC you get 6 Msamples/s in both directions. >>> >> >> >> I'm beginning to think the I2S bus may be the way to go if we can't >> make it work fast enough with bit-banging. It would require some more >> hardware work though. > > If that is 3MSPS, two ways, you are a long way from ever meeting that > SW bit banging. Even a SSC at 48MHz will need care, to keep the frame > overhead low. Use a cheap CPLD to wrap the details, and it will pay > for itself in saved cabling. > > -jg >I think you can run the SSC at 48 MHz and this has double buffered DMA support, so you should support 3 Msample/s in each direction using an I2S interface. If your ADC/DAC use a parallel bus, then you can add that CPLD or you can consider the AT91SAM9263, which has a second 16 bit databus and Dual memory to memory DMA support allowing you to easily meet bandwidth needs. The DMA can read/write to bus and to internal 16 kB SDRAM without cycle stealing from the CPU, since it is on the AHB bus matrix. -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic AB
Bit bang speed on AT91SAM9261 ARM processor
Started by ●March 20, 2007
Reply by ●March 21, 20072007-03-21
Reply by ●March 22, 20072007-03-22
Ulf Samuelsson wrote:> "Jim Granville" <no.spam@designtools.maps.co.nz> skrev i meddelandet >>If that is 3MSPS, two ways, you are a long way from ever meeting that >>SW bit banging. Even a SSC at 48MHz will need care, to keep the frame >>overhead low. Use a cheap CPLD to wrap the details, and it will pay >>for itself in saved cabling. >> >>-jg >> > > I think you can run the SSC at 48 MHz and this has > double buffered DMA support, so you should support 3 Msample/s in each > direction > using an I2S interface. > If your ADC/DAC use a parallel bus, then you can add that CPLD > or you can consider the AT91SAM9263, which has a second 16 bit > databus and Dual memory to memory DMA support allowing you to easily meet > bandwidth needs. > The DMA can read/write to bus and to internal 16 kB SDRAM without > cycle stealing from the CPU, since it is on the AHB bus matrix.I was thinking the SSC had a frame overhead simlar to SPI, but I see you can configure it many ways, and so use all clocks for data slots, which means there is effectvely no 'frame overhead'. I see SSC and CPLD as natural companions, for expansing these larger uC like Arm9, Avr32 etc, Depending on the ADC/DAC details, the OP may be able to MUX the IO dirn, and so save pins on the CPLD. -jg
