Hello, so I'm playing with http://f-cpu.seul.org/whygee/vspsim/ and developing a completely new instruction set, along with an architecture, tools etc... in JavaScript (before I translate to C and VHDL). An overall description of the core is available at http://f-cpu.seul.org/whygee/vspsim/doc/vsp.html [note that it is always under construction so some parts don't work] My question : Do you know of any processor architecture where the carry of the addition is not stored in a condition code register, but (instead) the core skips the next instruction(s) ? I have recently come to this idea because of many self-imposed limitations, like the existence of only one write port to the register set. And skipping is a nice alternative because the carry bit is often used as a condition for a jump, so the current solution jumps immediately. I know of many ISAs and architectures but I have not seen this before. Does anyone know a similar approach ? I post this here because this is more likely to be used in other small and embedded CPUs, rather than the large, server-scale CPUs of comp.arch. YG (you can reply to the address at the top of the first link of this page)
[Instruction Set Architecture] Skip on (no) carry
Started by ●April 14, 2007
Reply by ●April 15, 20072007-04-15
whygee wrote:> Hello, > > so I'm playing with http://f-cpu.seul.org/whygee/vspsim/ > and developing a completely new instruction set, > along with an architecture, tools etc... > in JavaScript (before I translate to C and VHDL). > An overall description of the core is available at > http://f-cpu.seul.org/whygee/vspsim/doc/vsp.html > [note that it is always under construction so some parts don't work] > > My question : > Do you know of any processor architecture where the carry > of the addition is not stored in a condition code register, > but (instead) the core skips the next instruction(s) ? > > I have recently come to this idea because of many self-imposed > limitations, like the existence of only one write port > to the register set. And skipping is a nice alternative > because the carry bit is often used as a condition for a jump, > so the current solution jumps immediately. > > I know of many ISAs and architectures but I have not seen > this before. Does anyone know a similar approach ? > I post this here because this is more likely to be used > in other small and embedded CPUs, > rather than the large, server-scale CPUs of comp.arch. > >As long as you have a one-instruction bit set, I can synthesize a carry bit so I'm mostly happy. There are times when I have done assembly language coding that I have found it convenient to wait a bit before I checked a condition bit, but I could probably cope with an add-skip-no-carry instruction (ASNC -- odd, but it'd do). If you're inventing an instruction set, remember that the PowerPC architecture has an EIEIO instruction. Please try to top it. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" gives you just what it says. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●April 15, 20072007-04-15
On Sun, 15 Apr 2007 02:14:09 +0200, whygee wrote:> so I'm playing with http://f-cpu.seul.org/whygee/vspsim/With regards to SHR, SAR, SHL, ROL, ROR, are ROL and ROR _really_ necessary? Not trying to discourage you from implementing them. My reason for asking is that I playing with a compact 16-bit design, and I looked at those and decided that I could sacrifice them. Regards, Paul.
Reply by ●April 15, 20072007-04-15
whygee wrote:> Hello, > > so I'm playing with http://f-cpu.seul.org/whygee/vspsim/ > and developing a completely new instruction set, > along with an architecture, tools etc... > in JavaScript (before I translate to C and VHDL). > An overall description of the core is available at > http://f-cpu.seul.org/whygee/vspsim/doc/vsp.html > [note that it is always under construction so some parts don't work] > > My question : > Do you know of any processor architecture where the carry > of the addition is not stored in a condition code register, > but (instead) the core skips the next instruction(s) ?I think you have a variable-length skip - which is a good idea. IIRC the COP8 had a packed jump, that was only 1 byte, and of limited reach (but efficent). Another benefit of a short-skip opcode, is for a core you wish to feed from Serial memory : SPI Flash is getting faster all the time [Winbond have 150MBd streaming], so the sequential access time is reasonable, but a branch is more costly. That means a skip makes sense, as it does not spawn a new address, and for small distances, that is faster than the jump.> > I have recently come to this idea because of many self-imposed > limitations, like the existence of only one write port > to the register set. And skipping is a nice alternative > because the carry bit is often used as a condition for a jump, > so the current solution jumps immediately. > > I know of many ISAs and architectures but I have not seen > this before. Does anyone know a similar approach ? > I post this here because this is more likely to be used > in other small and embedded CPUs, > rather than the large, server-scale CPUs of comp.arch.Some CPUs have conditional fields in the opcodes, which mean they can skip. It tends to be wasteful, as this is not often needed, but the CC bits come along for the ride anyway. I've also seen Conditional RET encoded, which used an otherwise unused field from the conditional jump variants, and that looked like a useful idea - esp. for assembler coding. Have you looked at the Lattice Mico8, and PicoBlaze / PacoBlaze SoftCPUs - they have some good 'compact' ideas. -jg
Reply by ●April 15, 20072007-04-15
whygee wrote:> Hello, > > so I'm playing with http://f-cpu.seul.org/whygee/vspsim/ > and developing a completely new instruction set, > along with an architecture, tools etc... > in JavaScript (before I translate to C and VHDL). > An overall description of the core is available at > http://f-cpu.seul.org/whygee/vspsim/doc/vsp.html > [note that it is always under construction so some parts don't work] > > My question : > Do you know of any processor architecture where the carry > of the addition is not stored in a condition code register, > but (instead) the core skips the next instruction(s) ?There are quite a few processors that don't have a condition code register. For extended math yours is one approach but you can also use some form of chained multiprecision math. Multiprecision operations with 32 bit processors probably could be dropped with very little impact on most applications.> I have recently come to this idea because of many self-imposed > limitations, like the existence of only one write port > to the register set. And skipping is a nice alternative > because the carry bit is often used as a condition for a jump, > so the current solution jumps immediately.Conceptually skip and conditional skip are powerful tools that can be used in clever combinations. Generally more skip conditions can be used than conventional conditional branches. A lot of thought needs to be put into what happens with sequential skip instructions. Is a skip treated as a pre-another instruction or a separate instruction? w..
Reply by ●April 15, 20072007-04-15
Paul Taylor wrote:> With regards to SHR, SAR, SHL, ROL, ROR, are ROL and ROR _really_ > necessary? Not trying to discourage you from implementing them. My reason > for asking is that I playing with a compact 16-bit design, and I looked at > those and decided that I could sacrifice them. >You can certainly sacrifice left operations. Right operations will depend a lot on the rest of the instruction set. A single barrel rotate can replace them all. w..
Reply by ●April 15, 20072007-04-15
Jim Granville wrote:> I think you have a variable-length skip - which is a good idea. > IIRC the COP8 had a packed jump, that was only 1 byte, and of > limited reach (but efficent). > > Another benefit of a short-skip opcode, is for a core you > wish to feed from Serial memory : SPI Flash is getting faster > all the time [Winbond have 150MBd streaming], so the sequential > access time is reasonable, but a branch is more costly. > That means a skip makes sense, as it does not spawn a new address, > and for small distances, that is faster than the jump.The COP8 is a remarkably compact instruction set. (We wrote a C compiler for it) 1) It used a lot of the instruction space for jumps and calls. 31 opcodes were used for branches you referred to as was a 2 byte in page branch and a 3 byte branch anywhere. It had 2 and 3 byte calls 2) The COP8 has a swap instead of a store (But does have a load). The swap saves a lot of temp space operations in expression evaluation. 3) The COP8 was implemented as a bit serial alu which made swap a very low cost instruction to implement. Most RMW instructions are very low cost bit serial (INC,DEC CLR set to 1 -1 for example) 4) The interrupt service in the COP8 is worth looking at. It is implemented as a combination of minimum hardware and specialized instructions to create a vectored interrupt system. Most of the logic is software. 5) Several processors have software I/O devices SX is well known. One that should also be looked at is how the Z8 handled its serial port. w.. w..
Reply by ●April 15, 20072007-04-15
On Sun, 15 Apr 2007 08:07:24 -0400, Walter Banks wrote:> You can certainly sacrifice left operations. Right operations will depend a > lot on the rest of the instruction set. A single barrel rotate can replace > them > all.I tentatively decided to have a shrc, shlc and shra - shrift right through carry, shift left through carry, and shift right arithmetic. I decided on just those three because I figured that the shift operations don't get used that much - mostly to multiply or divide by two on occasion. However, using this scheme, shifting logically takes two instructions - a clear carry instruction followed by the shrc/shrl instruction. But I can live with that. It means my instruction set is a bit smaller - I have taken this approach through the whole design. The reason why I said tentatively above is because I haven't done that much assembly language programming especially of late, and as I progress the design, bad decisions will of course need to be put right. Regards, Paul.
Reply by ●April 15, 20072007-04-15
Paul Taylor wrote:> On Sun, 15 Apr 2007 08:07:24 -0400, Walter Banks wrote: > > > You can certainly sacrifice left operations. Right operations will depend a > > lot on the rest of the instruction set. A single barrel rotate can replace > > them all. > > I tentatively decided to have a shrc, shlc and shra - shrift right through > carry, shift left through carry, and shift right arithmetic. I decided on > just those three because I figured that the shift operations don't get > used that much - mostly to multiply or divide by two on occasion. However, > using this scheme, shifting logically takes two instructions - a clear > carry instruction followed by the shrc/shrl instruction. But I can live > with that. It means my instruction set is a bit smaller - I have taken > this approach through the whole design.I have found that ASR is more important for general purpose computing that either LSR or ROR. I have dealt with many processors that did not have shift with carry and some that did not. Either is not a particularly big problem for code generation. I did not explain my barrel shift point earlier. Barrel shift or rotate is a very effective method of field extraction. w..
Reply by ●April 15, 20072007-04-15
