Problem with writing values to SRAM from XMD

Started by Roman April 25, 2007
Hello!

I am using a board with Virtex4 PPC405, external asynchronous SRAM
memory and EDK 8.2i. If application program resides in BRAM and I want
to write and read from SRAM, it is only possible if there is
instruction and data cache enebled and I add XCache_EnableCache in the
beginning of the code. So far it works. Then I tried to run
application from SRAM. So I generated linker script telling that the
program should be in SRAM. After I launched XMD and entered

dow executable.elf
run

it didn't work. When I tried to read downloaded code by mrd command
from SRAM, it showed zero values.
Furthermore, I tried to explicitly write a value to SRAM with mwr
command and read it afterwards, it showed zero value again.

So I thought the problem is that cache is still not enabled (because
code is not running and XCache_EnableCache function was not executed).
Then I set in XMD debug options "Set XMD memory map for  PPC405
features" where it is possible to enable caches, but it didn't help.

Parameter C_INCLUDE_BURST_CACHELN_SUPPORT in .mhs file is set to 1.

Does anybody have any suggestions what it could be?
Thanks in advance!

Best regards
Roman

On Apr 25, 11:37 am, Roman <plyas...@googlemail.com> wrote:
> Hello! > > I am using a board with Virtex4 PPC405, external asynchronous SRAM > memory and EDK 8.2i. If application program resides in BRAM and I want > to write and read from SRAM, it is only possible if there is > instruction and data cache enebled and I add XCache_EnableCache in the > beginning of the code. So far it works. Then I tried to run > application from SRAM. So I generated linker script telling that the > program should be in SRAM. After I launched XMD and entered > > dow executable.elf > run > > it didn't work. When I tried to read downloaded code by mrd command > from SRAM, it showed zero values. > Furthermore, I tried to explicitly write a value to SRAM with mwr > command and read it afterwards, it showed zero value again. > > So I thought the problem is that cache is still not enabled (because > code is not running and XCache_EnableCache function was not executed). > Then I set in XMD debug options "Set XMD memory map for PPC405 > features" where it is possible to enable caches, but it didn't help. > > Parameter C_INCLUDE_BURST_CACHELN_SUPPORT in .mhs file is set to 1. > > Does anybody have any suggestions what it could be? > Thanks in advance! > > Best regards > Roman
One way to track down the problem is to look at the sram lines with chipscope stimulating it with mwr, mrd. It could be that you were fooled in the first example, and data reads and writes looked good because they were being accessed via the cache only, and not beiIng posted to the sram. I believe chipscope is a good investment for what you are doing. A free evaluation is available from Xilinx. Newman
On Apr 26, 12:03 pm, Newman <newman5...@yahoo.com> wrote:
> On Apr 25, 11:37 am, Roman <plyas...@googlemail.com> wrote: > > > > > Hello! > > > I am using a board with Virtex4 PPC405, external asynchronousSRAM > > memory and EDK 8.2i. If application program resides in BRAM and I want > > to write and read fromSRAM, it is only possible if there is > > instruction and data cache enebled and I add XCache_EnableCache in the > > beginning of the code. So far it works. Then I tried to run > > application fromSRAM. So I generated linker script telling that the > > program should be inSRAM. After I launched XMD and entered > > > dow executable.elf > > run > > > it didn't work. When I tried to read downloaded code by mrd command > > fromSRAM, it showed zero values. > > Furthermore, I tried to explicitly write a value toSRAMwith mwr > > command and read it afterwards, it showed zero value again. > > > So I thought the problem is that cache is still not enabled (because > > code is not running and XCache_EnableCache function was not executed). > > Then I set in XMD debug options "Set XMD memory map for PPC405 > > features" where it is possible to enable caches, but it didn't help. > > > Parameter C_INCLUDE_BURST_CACHELN_SUPPORT in .mhs file is set to 1. > > > Does anybody have any suggestions what it could be? > > Thanks in advance! > > > Best regards > > Roman > > One way to track down the problem is to look at thesramlines with > chipscope stimulating it with mwr, mrd. It could be that you were > fooled in the first example, and data reads and writes looked good > because they were being accessed via the cache only, and not beiIng > posted to thesram. > > I believe chipscope is a good investment for what you are doing. A > free evaluation is available from Xilinx. > > Newman
Thanks a lot! There was a problem with physical connection to SRAM.