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verilog HDL problem

Started by nasi...@gmail.com June 7, 2007
what is the error in the following code. in it the main module is
"test". in that module's "always" block another module "counter" is
called. but it shows error. how can i solve the problem? how can i
call another module in always block?


module counter(clock, reset, count);
    input clock, reset;
    output [3:0] count;

    reg [3:0] next_count,count;

    always@*
    begin
        if(count<15)
            next_count=count+4'd1;
        else
            next_count=count;
    end

    always@(posedge clock)
    begin
        if(reset)
           count<=4'd0;
        else
           count<=next_count;
    end
endmodule


module test(clock,reset,count);
input clock, reset;
output [3:0] count;
reg [3:0] count;
always @(clock)
    counter(clock, reset, count);
endmodule

nasif4003@gmail.com wrote:
> what is the error in the following code. in it the main module is > "test". in that module's "always" block another module "counter" is > called. but it shows error. how can i solve the problem? how can i > call another module in always block? >
Hi there, First of all, there is a newsgroup for Verilog discussions: comp.lang.verilog (and I noticed that you just post your question there as well). You cannot put a module in a process that only execute at clock edge. Try think that the counter module is a hardware, and you can't make it appear only at clock edge, it exist in the design all the time. So instead of putting it in a process, you should instantiate it. module test(clock,reset,count); input clock, reset; output [3:0] count; // reg [3:0] count; // This line is removed because // it is not controlled by a process. // Instantiate counter counter counter1(clock, reset, count); endmodule If you want to do a number of processing inside a process, you could use "function". Google "Verilog" and "function" should come up with lots of examples. Hope this help. regards, Joseph
> > module counter(clock, reset, count); > input clock, reset; > output [3:0] count; > > reg [3:0] next_count,count; > > always@* > begin > if(count<15) > next_count=count+4'd1; > else > next_count=count; > end > > always@(posedge clock) > begin > if(reset) > count<=4'd0; > else > count<=next_count; > end > endmodule > > > module test(clock,reset,count); > input clock, reset; > output [3:0] count; > reg [3:0] count; > always @(clock) > counter(clock, reset, count); > endmodule >